USB7056 datasheet(18/55 Pages) MICROCHIP

18 / 55 page

USB7056

DS00002675F-page 18

 2022 Microchip Technology Inc. and its subsidiaries

DP1_DISCHARGE

I/O12

Port 1 DISCHARGE enable

PRT_CTL6

I/O12

(PU)

Port 6 power enable / overcurrent sense

When the downstream port is enabled, this pin is set as an input with an

internal pull-up resistor applied. The internal pull-up enables power to the

downstream port while the pin monitors for an active low overcurrent signal

assertion from an external current monitor on USB port 6.

This pin will change to an output and be driven low when the port is dis-

abled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the USB 2.0

and USB 3.2 portions of the port. When PortSplit is enabled, this

signal controls the USB 2.0 portion of the port only.

PRT_CTL5

I/O12

(PU)

Port 5 power enable / overcurrent sense

When the downstream port is enabled, this pin is set as an input with an

internal pull-up resistor applied. The internal pull-up enables power to the

downstream port while the pin monitors for an active low overcurrent signal

assertion from an external current monitor on USB port 5.

This pin will change to an output and be driven low when the port is dis-

abled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the USB 2.0

and USB 3.2 portions of the port. When PortSplit is enabled, this

signal controls the USB 2.0 portion of the port only.

PRT_CTL4

I/O12

(PU)

Port 4 power enable / overcurrent sense

When the downstream port is enabled, this pin is set as an input with an

internal pull-up resistor applied. The internal pull-up enables power to the

downstream port while the pin monitors for an active low overcurrent signal

assertion from an external current monitor on USB port 4.

This pin will change to an output and be driven low when the port is dis-

abled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the USB 2.0

and USB 3.2 portions of the port. When PortSplit is enabled, this

signal controls the USB 2.0 portion of the port only.

PRT_CTL3

I/O12

(PU)

Port 3 power enable / overcurrent sense

When the downstream port is enabled, this pin is set as an input with an

internal pull-up resistor applied. The internal pull-up enables power to the

downstream port while the pin monitors for an active low overcurrent signal

assertion from an external current monitor on USB port 3.

This pin will change to an output and be driven low when the port is dis-

abled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the USB 2.0

and USB 3.2 portions of the port. When PortSplit is enabled, this

signal controls the USB 2.0 portion of the port only.

TABLE 3-6:

PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)

Function

Buffer

Type

Description

USB7056 数据表(PDF) 18 Page - Microchip Technology

USB7056 数据表(HTML) 18 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

数据表下载

链接网址

USB7056 数据表(PDF) 18 Page - Microchip Technology

USB7056 数据表(HTML) 18 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

数据表 下载

链接网址

数据表下载