USB7056 datasheet(19/55 Pages) MICROCHIP

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DS00002675F-page 19

USB7056

PRT_CTL2

I/O12

(PU)

Port 2 power enable / overcurrent sense

When the downstream port is enabled, this pin is set as an input with an

internal pull-up resistor applied. The internal pull-up enables power to the

downstream port while the pin monitors for an active low overcurrent signal

assertion from an external current monitor on USB port 2.

This pin will change to an output and be driven low when the port is dis-

abled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the USB 2.0

and USB 3.2 portions of the port. When PortSplit is enabled, this

signal controls the USB 2.0 portion of the port only.

PRT_CTL1

I/O12

(PU)

Port 1 power enable / overcurrent sense

When the downstream port is enabled, this pin is set as an input with an

internal pull-up resistor applied. The internal pull-up enables power to the

downstream port while the pin monitors for an active low overcurrent signal

assertion from an external current monitor on USB port 1.

This pin will change to an output and be driven low when the port is dis-

abled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the USB 2.0

and USB 3.2 portions of the port. When PortSplit is enabled, this

signal controls the USB 2.0 portion of the port only.

PRT_CTL4_U3

O12

Port 4 USB 3.2 PortSplit power enable

This signal is an active high control signal used to enable to the USB 3.2

portion of the downstream port 4 when PortSplit is enabled. When PortSplit

is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded USB 3.2

device.

PRT_CTL3_U3

O12

Port 3 USB 3.2 PortSplit power enable

This signal is an active high control signal used to enable to the USB 3.2

portion of the downstream port 3 when PortSplit is enabled. When PortSplit

is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded USB 3.2

device.

PRT_CTL2_U3

O12

Port 5 USB 3.2 PortSplit power enable

This signal is an active high control signal used to enable to the USB 3.2

portion of the downstream port 5 when PortSplit is enabled. When PortSplit

is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded USB 3.2

device.

GPIOx

I/O12

General Purpose Inputs/Outputs

(x = 70-71, 83)

TABLE 3-6:

PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)

Function

Buffer

Type

Description

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USB7056 数据表(PDF) 19 Page - Microchip Technology

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Html Pages

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