| 数据搜索系统,热门电子元器件搜索 |
|
USB7056 数据表(PDF) 13 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
USB7056 数据表(HTML) 13 Page - Microchip Technology |
|
13 / 55 page ![]() 2022 Microchip Technology Inc. and its subsidiaries DS00002675F-page 13 USB7056 Analog Test ATEST A Analog test pin. This signal is used for test purposes and must either be left unconnected or tied to ground. External 25 MHz Crystal Input XTALI ICLK External 25 MHz crystal input External 25 MHz Reference Clock Input CLKIN ICLK External reference clock input. The device may alternatively be driven by a single- ended clock oscillator. When this method is used, XTALO should be left unconnected. External 25 MHz Crystal Output XTALO OCLK External 25 MHz crystal output Configuration Straps Port 6-1 D+ Disable Configuration Strap PRT_DIS_P[6:1] I Port 6-1 D+ Disable Configuration Strap. These configuration straps are used in conjunction with the corresponding PRT_DIS_M[6:1] straps to disable the related port (6-1). See Note 3-1. Both USB data pins for the corresponding port must be tied to 3.3V to disable the associated downstream port. Port 6-1 D- Disable Configuration Strap PRT_DIS_M[6:1] I Port 6-1 D- Disable Configuration Strap. These configuration straps are used in conjunction with the corresponding PRT_DIS_P[6:1] straps to disable the related port (6-1). See Note 3-1. Both USB data pins for the corresponding port must be tied to 3.3V to disable the associated downstream port. Non-Removable Ports Configuration Strap CFG_NON_REM I Non-Removable Ports Configuration Strap. This configuration strap controls the number of reported non-removable ports. See Note 3-1. Battery Charging Configuration Strap CFG_BC_EN I/O12 Battery Charging Configuration Strap. This configuration strap controls the number of BC 1.2 enabled downstream ports. See Note 3-1. Device Mode Configuration Straps 3-1 CFG_STRAP[3:1] I Device Mode Configuration Straps 3-1. These configuration straps are used to select the device’s mode of operation. See Note 3-1. Power/Ground +3.3V I/O Power Supply Input VDD33 P +3.3 V power and internal regulator input. TABLE 3-1: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |