ADP1031ACPZ-3-R7 datasheet(26/38 Pages) AD

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ADP1031

Data Sheet

Rev. A | Page 26 of 38

INVERTING REGULATOR

Inverting Regulator Operation

The inverting, dc-to-dc regulator in the ADP1031 uses a current

mode controlled scheme, operating at a fixed frequency set by

an internal oscillator. Current mode uses a fast inner current

controlled loop to regulate the peak inductor current and a slower

outer loop to adjust the current loop to regulate the output voltage.

At the start of each oscillator cycle, the high-side MOSFET switch

turns on, applying the input voltage to one end of the inductor,

which normally causes the inverting regulator inductor current

(IINV_INDUCTOR) to increase until the current sense signal crosses

the peak inductor current threshold that turns off the MOSFET

switch. The error amplifier output sets this threshold. During the

high-side MOSFET off time, the inductor current declines through

the low-side MOSFET switch until either the next oscillator

clock pulse starts a new cycle, which results in CCM operation, or

the inductor current reaches zero, the low-side MOSFET switch

is turned off, and the control system waits for the next oscillator

clock pulse to start a new cycle, resulting in DCM operation.

Under light load conditions, the regulator can skip pulses to

maintain regulation and increase power conversion efficiency.

Inverting Regulator UVLO

The inverting, dc-to-dc regulator of the ADP1031 features an

internal UVLO circuit that monitors the input voltage to the

regulator or VOUT1. If the voltage at VOUT1 drops below the

internal threshold level of 4.5 V, the regulator turns off. If the

output of VOUT1 rises above the internal threshold, the

regulator soft start period initiates, and the regulator enables.

Inverting Regulator Soft Start

The inverting, dc-to-dc regulator in the ADP1031 includes soft

start circuitry that ramps the output voltage in a controlled

manner during startup, thereby limiting the inrush current.

Inverting Regulator Current-Limit Protection

The inverting, dc-to-dc regulator in the ADP1031 includes a

current-limit protection circuit to limit the amount of forward

current through the high-side MOSFET switch. The inductor peak

current is monitored cycle by cycle to detect an overload condition.

When the overload condition occurs, the current-limit protection

limits the peak inductor current to ILIM (INVERTER), resulting in a

drop in the output voltage.

Inverting Regulator OVP

The inverting, dc-to-dc regulator of the ADP1031 features an

OVP circuit that monitors the voltage on the FB3 pin. If the

voltage on this pin falls below VFB3 by 10%, the inverting regulator

stops switching until the voltage rises above the threshold again.

Inverting Regulator Active Pull-Down Resistor

The inverting regulator has an active pull-down resistor that

discharges the output capacitor when the output of VOUT1 is

between 1.23 V and 4.5 V. The pull-down resistor connects

between VOUT3 and SGND2.

POWER GOOD

The ADP1031 provides a push pull, power-good output to

indicate when the three isolated output voltage rails are valid.

The PWRGD pin pulls high when the voltages on the three

supplies are within the respective power-good threshold limits.

POWER-UP SEQUENCE

The power-up sequence is as follows (see Figure 66):

1. The flyback regulator powers up first (see 1 in Figure 66).

2. When VOUT1 rises above the lower power-good threshold

(VPG_FLYBACK_LL), the buck regulator turns on (see 2 in Figure 66).

3. When the buck regulator output (VOUT2) rises above the

lower power-good threshold (VPG_BUCK_LL), the inverting

regulator turns on (see 3 in Figure 66).

4. PWRGD is driven high when the inverting regulator output

(VOUT3) is below the power-good threshold,

VPG_INVERTER_LL (see 4 in Figure 66).

5. If any of the three analog supplies move outside the power-

good threshold ranges, PWRGD drives low after a short

deglitch delay (see 5 in Figure 66).

HIGH

LOW

PWRGD

VOUT3

VOUT2

VINP

VOUT1

VPG_FLYBACK_UL

VPG_FLYBACK_LL

VPG_BUCK_LL

VPG_INVERTER_LL

Figure 66. Power-Up Sequencing and PWRGD

OSCILLATOR AND SYNCHRONIZATION

A phase-locked loop (PLL)-based oscillator generates the internal

clock for the flyback, buck, and inverter regulators and offers an

internally generated frequency or external clock synchronization.

Connect the SYNC pin as describe in Table 11 to configure the

switching frequency. For external synchronization, connect the

SYNC pin to a suitable clock source. The PLL locks to an input

clock within the range specified by fSYNC.

Table 11. Sync Pin Functionality

Switching Frequency (fSW)

SYNC Pin State, fSYNC

Flyback

Buck

Inverter

Low or High

250 kHz

125 kHz

350 kHz to 750 kHz

fSYNC ÷ 2

fSYNC ÷ 4

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