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ADP1031ACPZ-3-R7 数据表(PDF) 12 Page - Analog Devices |
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ADP1031ACPZ-3-R7 数据表(HTML) 12 Page - Analog Devices |
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12 / 38 page  ADP1031 Data Sheet Rev. A | Page 12 of 38 Pin No. Mnemonic Isolation Domain Direction Description 21 SGPI3 Slave Input General-Purpose Input 3. This pin is paired with MGPO3. 22 SGPO2 Slave Output General-Purpose Output 2. This pin is paired with MGPI2. 23 SGPO1 Slave Output General-Purpose Output 1. This pin is paired with MGPI1. 24 DNC Slave Not applicable Do Not Connect. Do not connect to this pin. 25 DNC Slave Not applicable Do Not Connect. Do not connect to this pin. 26 DNC Slave Not applicable Do Not Connect. Do not connect to this pin. 27 SGND2 Slave Return Slave Domain Ground Connection. This pin can be left unconnected. 28 PGNDP Field power Return Ground Return for Flyback Regulator Power Supply. 29 SWP Field power Not applicable Flyback Regulator Switching Node. Primary side transformer connection. 30 VINP Field power Power Flyback Regulator Supply Voltage. Connect a minimum of 3.3 µF capacitor from VINP to PGNDP. 31 EN Field power Input Precision Enable. Compare the EN pin to an internal precision reference to enable the flyback regulator output. 32 SLEW Field power Input Flyback Regulator Slew Rate Control. The SLEW pin sets the slew rate for the SWP driver. For the fastest slew rate (best efficiency), leave the SLEW pin open. For the normal slew rate, connect the SLEW pin to VINP. For the slowest slew rate (best EMI performance), connect the SLEW pin to GNDP. 33 GNDP Field power Return Field Power Signal Ground Connection. 34 MGND Master Return Master Domain Power Ground Connection. 35 PWRGD Master Return Power Good. This pin indicates when the secondary side supplies are within their programmed range. 36 MGPI1 Master Input General-Purpose Input 1. This pin is paired with SGPO1. 37 MGPI2 Master Input General-Purpose Input 2. This pin is paired with SGPO2. 38 MGPO3 Master Output General-Purpose Output 3. This pin is paired with SGPI3. 39 MVDD Master Power Master Domain Power. Connect a 100 nF decoupling capacitor from MVDD to MGND. 40 MCK Master Input SPI Clock Input from the Master Controller. Paired with SCK. On the slave domain, this pin drives SCK. 41 MO Master Input SPI Data Input Going to Slave MO and SI Line. Paired with SI. On the slave domain, this pin drives SI. EPGNDP Field power Return PGNDP Exposed Pad. This pad is internally connected to PGNDP. EPGNDM Master Return MGND Exposed Pad. This pad is internally connected to MGND. EPGND2 Slave Return SGND Exposed Pad. This pad is internally connected to SGND. |
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