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ADP1031ACPZ-3-R7 数据表(PDF) 4 Page - Analog Devices

部件名 ADP1031ACPZ-3-R7
功能描述  Three-Channel, Isolated Micropower Management Unit with Seven Digital Isolators
PDF  38 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1031ACPZ-3-R7 数据表(HTML) 4 Page - Analog Devices

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ADP1031
Data Sheet
Rev. A | Page 4 of 38
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
THERMAL SHUTDOWN
Threshold
TSHDN
150
°C
Hysteresis
THYS
15
°C
PRECISION ENABLE
Rising Input Threshold
VEN_RISING
1.10
1.135
1.20
V
Input Hysteresis
VEN_HYST
100
mV
Leakage Current
0.03
0.5
µA
VEN = VINP
POWER GOOD
Power-Good Threshold
Flyback Regulator
Lower Limit
VPG_FLYBACK_LL
87.5
90
92.5
%
Fixed and adjustable output
versions
Upper Limit
VPG_FYLBACK_UL
107.5
110
112.5
%
Fixed and adjustable output
versions
Buck Regulator
Lower Limit
VPG_BUCK_LL
87.5
90
92.5
%
Upper Limit
VPG_BUCK_UL
107.5
110
112.5
%
Inverting Regulator
Lower Limit
VPG_INVERTER_LL
87.5
90
92.5
%
Upper Limit
VPG_INVERTER_UL
107.5
110
112.5
%
Glitch Rejection
1.36
µs
Glitch of ±15% of the typical
output
Output Voltage
Logic High
VPWRGD_OH
VMVDD −
0.4
V
PWRGD current (IPWRGD) = −1 mA
Logic Low
VPWRGD_OL
0.4
V
IPWRGD = 1 mA
SLEW
Voltage Level Threshold
Slow Slew Rate
0.8
V
Normal Slew Rate
2
V
Input Current
Slow Slew Rate
−10
µA
Slew voltage (VSLEW) = 0 V to 0.8 V
Normal Slew Rate
10
µA
VSLEW = 2 V to VINP
Fast Slew Rate
−1
+1
µA
SLEW pin not connected
CLOCK SYNCHRONIZATION
SYNC Input
Input Clock
Range
fSYNC
350
750
kHz
Minimum On Pulse Width
tSYNC_MIN_ON
100
ns
Minimum Off Pulse Width
tSYNC_MIN_OFF
150
ns
High Logic
VH (SYNC)
1.3
V
Low Logic
VL (SYNC)
0.4
V
Leakage Current
−1
0.005
1
µA
SYNC voltage (VSYNC) = VSVDDx
FLYBACK REGULATOR
Output Voltage Range
VOUT1 (ADJ)
6
28
V
ADP1031ACPZ-1,
ADP1031ACPZ-2, and
ADP1031ACPZ-3
VOUT1 (FIXED)
24
V
ADP1031ACPZ-4
VOUT1 (FIXED)
21
V
ADP1031ACPZ-5
Output Voltage Accuracy
−1.5
+1.5
%
Fixed output options



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