ADPA7008AEHZ-R7 datasheet(18/28 Pages) AD

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Data Sheet

ADPA7008

THEORY OF OPERATION

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Rev. 0 | 18 of 28

The architecture of the ADPA7008, a medium power amplifier, is

shown in Figure 67. The ADPA7008 uses two cascaded, four-stage

amplifiers operating in quadrature between six 90° hybrids.

The input signal is divided evenly into two, and then each signal

is divided into two again. Each of these new paths are amplified

through four independent gain stages. The amplified signals are

then combined at the output. This balanced amplifier approach

forms an amplifier with a combined gain of 17.5 dB and a PSAT

value of 31 dBm.

The quadrature hybrid couplers ensure good broadband input and

output return loss matching across the full 20 GHz to 54 GHz

frequency range of the ADPA7008. See the application circuits

shown in Figure 68 and Figure 69 for further details on biasing the

various blocks.

A portion of the RF output signal is directionally coupled to a diode

for detection of the RF POUT. When the diode is dc biased, the

diode rectifies the RF power and makes the RF power available

for measurement as a dc voltage at VDET. To allow temperature

compensation of VDET, an identical and symmetrically located cir-

cuit, minus the coupled RF power, is available via VREF. Taking the

difference of VREF − VDET provides a temperature compensated

signal that is proportional to the RF output (see Figure 67).

Figure 67. ADPA7008 Architecture

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