ADPA7008AEHZ-R7 datasheet(19/28 Pages) AD

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Data Sheet

ADPA7008

APPLICATIONS INFORMATION

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Rev. 0 | 19 of 28

Figure 68 shows the basic connections for operation when the gate

voltage is applied on the north side of the device to Pin 4 (VGG1).

Figure 69 shows the basic connections for operation when the gate

voltage is applied on the south side to Pin 10 (VGG2). While the

gate voltage bias signal can be applied to either VGG1 or to VGG2

(the unused pin is left open), the drain supply must be applied to

all VDDx pins. The power supply decoupling scheme shown can be

simplified by combining the larger capacitance values. For example,

C13 and C14 can be combined into a single 4.7 μF capacitor (C18

and C29 can be combined in the same manner). Each VDDx pin

must have at least one dedicated 100 pF capacitor.

All measurements for this device were taken using the application

circuit (see Figure 68 ).

The recommended power-up bias sequence is as follows:

1. Connect GND to RF and dc ground.

2. Set the gate bias voltages, VGG1 or VGG2, to −1.5 V.

3. Set all drain bias voltages, VDDx, to 5 V.

4. Increase the gate bias voltages, VGG1 or VGG2, to achieve an

IDQ of 1500 mA.

5. Apply the RF signal.

The recommended power-down bias sequence is as follows:

1. Turn off the RF signal.

2. Decrease the gate bias voltages, VGG1 or VGG2, to −1.5 V to

achieve an IDQ = 0 mA (approximately).

3. Decrease all the drain bias voltages, VDDx, to 0 V.

4. Increase the gate bias voltages, VGG1 or VGG2, to 0 V.

The VDD = 5 V and IDQ = 1500 mA bias conditions are recommend-

ed to optimize overall performance. Unless otherwise noted, the

data shown was taken using the recommended bias conditions

and basic connections schematic with north side gate biasing (see

Figure 68). See Figure 69 for the application circuit for the south

side gating biasing configuration.

Operation of the ADPA7008 at different bias conditions provides

performance that differs from what is shown in Table 1,

Table 2, Table 3, and Table 4. Biasing the ADPA7008 for higher

drain current typically results in higher P1dB and gain at the

expense of increased power consumption (see Table 9). Data

was taken for Table 9 at the following nominal bias conditions:

VDD = 5 V, TA = 25°C, and frequency = 36 GHz.

Table 9. Power Selection Table

IDQ (mA)

Gain (dB)

P1dB (dBm)

Output IP3 (dBm)

PDISS (W) at PSAT

VGGx (V)1

1300

17.7

30.1

40.4

7.7

−0.68

1500

18.4

30.3

39.2

7.9

−0.63

1700

18.8

30.6

36.9

8.0

−0.59

1 Adjust VGG1 from −1.5 V to 0.4 V to achieve the desired drain current.

TYPICAL APPLICATION CIRCUITS

Figure 68. Basic Connections for Operation with the North Side Gate Voltage Biasing

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