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MPC7410EC 数据表(PDF) 20 Page - NXP Semiconductors |
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MPC7410EC 数据表(HTML) 20 Page - NXP Semiconductors |
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20 / 56 page ![]() MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 20 Freescale Semiconductor Electrical and Thermal Characteristics 4.2.4 L2 Bus AC Specifications Table 10 provides the L2 bus interface AC timing specifications for the MPC7410 as defined in Figure 8 and Figure 9 for the loading conditions described in Figure 10. Table 10. L2 Bus Interface AC Timing Specifications At recommended operating conditions (see Table 3) Parameter Symbol 400, 450, 500 MHz Unit Notes Min Max L2SYNC_IN rise and fall time tL2CR and tL2CF —1.0 ns 1 Setup times: Data and parity tDVL2CH 1.5 — ns 2 Input hold times: Data and parity tDXL2CH —0.0 ns 2 Valid times: All outputs when L2CR[14–15] = 00 All outputs when L2CR[14–15] = 01 All outputs when L2CR[14–15] = 10 All outputs when L2CR[14–15] = 11 tL2CHOV — — — — 2.5 2.5 2.9 3.5 ns 3, 4 Output hold times All outputs when L2CR[14–15] = 00 All outputs when L2CR[14–15] = 01 All outputs when L2CR[14–15] = 10 All outputs when L2CR[14–15] = 11 tL2CHOX 0.4 0.8 1.2 1.6 — — — — ns 3 L2SYNC_IN to high impedance: All outputs when L2CR[14–15] = 00 All outputs when L2CR[14–15] = 01 All outputs when L2CR[14–15] = 10 All outputs when L2CR[14–15] = 11 tL2CHOZ — — — — 2.0 2.5 3.0 3.5 ns — Notes: 1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD. 2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins. 3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- Ω load (see Figure 10). 4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous BurstRAMs, L2CR[14–15] = 00 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14–15] = 10 is recommended. |
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