SWCS049E datasheet(53/144 Pages) TI

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TPS65911

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SWCS049S – JUNE 2010 – REVISED AUGUST 2018

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Detailed Description

Table 6-3. Boot Configuration: General Control Bits (continued)

BIT

DESCRIPTION

TPS65911

FIXED BOOT

EEPROM BOOT

EEPROM

AUTODEV_ON

0: PWRHOLD pin is used as PWRHOLD

feature.

1, PWRHOLD

pin is GPI

1: PWRHOLD pin is GPI. After power on,

DEV_ON set high internally, no processor

action required to keep supplies.

EEPROM

PWRDN_POL

0: PWRDN signal will be active-low.

Active-low

1: PWRDN signal will be active-high.

6.5.3

Control Signals

6.5.3.1

SLEEP

When none of the device SLEEP-disable conditions are met, a falling edge (default, or rising edge,

depending on the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the

device. A rising edge (default, or falling edge, depending on the programmed polarity) causes a transition

back to the ACTIVE state. This input signal is level-sensitive and no debouncing is applied.

While the device is in the SLEEP state, predefined resources are automatically set in their low-power

mode or off. Resources can be kept in their active mode (full-load capability) by programming the

SLEEP_KEEP_LDO_ON and the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per

power resource. If the bit is set to 1, then that resource stays in active mode when the device is in the

SLEEP state.

32KCLKOUT is also included in the SLEEP_KEEP_RES_ON register and the 32-kHz clock output is

maintained in the SLEEP state if the corresponding mask bit is set.

The status (low or high) of GPO0, GPO6, GPO7, and GPO8 are also controlled by the SLEEP signal, to

allow enabling and disabling of external resources during sleep.

6.5.3.2

PWRHOLD

The PWRHOLD pin can be used as a PWRHOLD signal input or as a general purpose input (GPI). The

mode is selected by the AUTODEV_ON bit, which is part of the boot configuration. When

AUTODEV_MODE = 0, the PWRHOLD feature is selected.

Configured as PWRHOLD, when none of the device POWER ON disable conditions are met, a high level

of this signal causes an OFF-to-ACTIVE state transition of the device and a low level causes a transition

back to the OFF state.

This input signal is level-sensitive and no debouncing is applied. The rising and/or falling edge of

PWRHOLD is highlighted through an associated interrupt if interrupt is unmasked.

When AUTODEV_ON = 1, the pin is used as a GPI. As a GPI, this input can generate a maskable

interrupt from a rising or falling edge of the input. When AUTODEV_ON = 1, a rising edge of

NRESPWRON also automatically sets the DEV_ON bit to 1 to keep supplies after the switch-on

sequence, thus removing the need for the processor to set the PWRHOLD signal or the DEV_ON bit.

6.5.3.3

BOOT1

This signal determines with which processor the device is working and, hence, which power-up sequence

is needed. For more details, see Section 5.21.2. No debouncing is present on this input signal.

6.5.3.4

NRESPWRON, NRESPWRON2

The NRESPWRON signal is used as the reset to the processor and is in the VDDIO domain. It is held low

until the ACTIVE state is reached. For detailed timing, see Section 5.21.2.

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