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TPS65911

SWCS049S – JUNE 2010 – REVISED AUGUST 2018

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Detailed Description

The NRESPWRON2 signal is a second reset output. It follows the state of NRESPWRON but has an

open-drain output with external pullup. The supply for the external pullup must not be activated before the

TPS65911 device is in control of the output state (that is, not earlier than during first power-up sequence

slot). In off mode, the NRESPWRON2 output has weak internal pulldown.

6.5.3.5

CLK32KOUT

This signal is the output of the 32K oscillator, which can be enabled or not during the power-on sequence,

depending on the boot mode. It can be enabled and disabled by register bit, during the ACTIVE state of

the device. The CLK32KOUT output can also be enabled or not during the SLEEP state of the device

depending on the programming of the SLEEPMASK register.

6.5.3.6

PWRON

The PWRON input is connected to an external button. If the device is in the OFF or SLEEP state, a

debounced falling edge (PWRON input low for minimum of 100 ms) causes an OFF-to-ACTIVE state or a

SLEEP-to-ACTIVE state transition of the device. If the device is in active mode, then a low level on this

signal generates an interrupt. If the PWRON signal is low for more than the PWON_TO_OFF_DELAY

delay and the corresponding interrupt is not acknowledged by the processor within 1 second, the device

goes into the OFF state. For PWRON behavior, see Figure 5-2 and Figure 5-3.

6.5.3.7

INT1

The INT1 signal (default active low) warns the host processor of any event that has occurred on the

TPS65911 device. The host processor can then poll the interrupt from the interrupt status register through

I2C to identify the interrupt source. A low level (default setting) indicates an active interrupt, highlighted in

the INT_STS_REG register. The polarity of INT1 can be set programming the IT_POL control bit. INT1

flag active is a POWER ON enable condition during a fixed delay, tDOINT1 (only), when the device is in the

OFF state (when NRESPWRON is low).

Any of the interrupt sources can be masked programming the INT_MSK_REG register. When an interrupt

is masked its corresponding interrupt status bit is still updated, but the INT1 flag is not activated. Interrupt

source masking can be used to mask a device switch-on event. Because interrupt flag active is a POWER

ON enable condition, during tDOINT1 delay, any interrupt not masked must be cleared to allow immediate

turn off of the device.

For a description of interrupt sources, see Table 6-5.

6.5.3.8

EN2 and EN1

EN2 and EN1 are the data and clock signals of the serial control interface dedicated to voltage scaling

applications.

These signals can also be programmed to be used as enable signals of one or several supplies, when the

device is on (NRESPWRON high). A resource assigned to EN2 or EN1 control automatically disables the

serial control interface.

Programming EN1_LDO_ASS_REG, EN2_LDO_REG, and SLEEP_KEEP_LDO_ON_REG registers: EN1

and EN2 signals can be used to control the turn on/off or SLEEP state of any LDO-type supplies.

Programming EN1_SMPS_ASS_REG, EN2_SMPS_ASS_REG, and SLEEP_KEEP_RES_ON registers:

EN1 and EN2 signals can be used to control the turn on/off or LOW-POWER state (PFM mode) of SMPS-

type supplies.

The EN2 and EN1 signals can be used to set the output voltage of VDD1 and VDD2 SMPS from a roof to

floor

value,

preprogrammed

the

VDD1_OP_REG,

VDD2_OP_REG

and

VDD1_SR_REG,

VDD2_SR_REG registers.

When a supply is controlled through the EN1 or EN2 signals, its state is no longer driven by the device

SLEEP state.

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