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SWCS049E 数据表(PDF) 63 Page - Texas Instruments

部件名 SWCS049E
功能描述  TPS65911 Integrated Power Management Unit Top Specification
PDF  144 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SWCS049E 数据表(HTML) 63 Page - Texas Instruments

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SWCS049-021
D
A
D
6
D
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5
D
A
D
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2
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1
D
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0
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7
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SDA
SCL
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SWCS049-020
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DAD: Device address
RAD: Register address
DAT: Data
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Slave drives SDA
Master drives SDA
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TPS65911
www.ti.com
SWCS049S – JUNE 2010 – REVISED AUGUST 2018
Submit Documentation Feedback
Product Folder Links: TPS65911
Detailed Description
Copyright © 2010–2018, Texas Instruments Incorporated
6.12.1
Access Protocols
For compatibility, the I2C interfaces in the TPS65911 device use the same read/write protocol as other TI
power ICs, based on an internal register size of 8 bits. Supported transactions are described in the
following sections.
6.12.1.1 Single Byte Access
A write access is initiated by a first byte including the address of the device (7 MSBs) and a write
command (LSB), a second byte provides the address (8 bits) of the internal register, and the third byte
represents the data to be written in the internal register, see Figure 6-7.
A read access is initiated by:
•
A first byte, including the address of the device (7 MSBs) and a write command (LSB)
•
A second byte, providing the address (8 bits) of the internal register
•
A third byte, including again the device address (7 MSBs) and the read command (LSB)
The device replies by sending a fourth byte representing the content of the internal register (see
Figure 6-8).
Figure 6-7. I2C Write Access Single Byte
Figure 6-8. I2C Read Access Single Byte
6.12.1.2 Multiple Byte Access to Several Adjacent Registers
A write access is initiated by:
•
A first byte, including the address of the device (7 MSBs) and a write command (LSB)
•
A second byte, providing the base address (8 bits) of the internal registers
The following N bytes represent the data to be written in the internal register starting at the base address
and incremented by one at each data byte (see Figure 6-9).
A read access is initiated by:
•
A first byte, including the address of the device (7 MSBs) and a write command (LSB)
•
A second byte, providing the base address (8 bits) of the internal register
•
A third byte, including again the device address (7 MSBs) and the read command (LSB)
The device replies by sending a fourth byte, representing the content of the internal registers, starting at
the base address and next consecutive ones (see Figure 6-10).



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