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SWCS049G 数据表(PDF) 95 Page - Texas Instruments |
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SWCS049G 数据表(HTML) 95 Page - Texas Instruments |
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95 / 144 page ![]() 95 TPS65911 www.ti.com SWCS049S – JUNE 2010 – REVISED AUGUST 2018 Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-57. DEVCTRL2_REG Address Offset 0x40 Instance Reset Domain: GENERAL RESET TSLOT_LENGTH: TURN OFF RESET Description Device control register Type RW 7 6 5 4 3 2 1 0 Reserved DCDC_SLEEP _LVL TSLOT_LENGTH SLEEPSIG_ POL PWON_LP_ OFF PWON_LP_ RST IT_POL Bits Field Name Description Type Reset 7 Reserved RO R returns 0s 0 6 DCDC_SLEEP_LVL When 1, DCDC output level in SLEEP mode is VDDx_SR_REG, to be other than 0 V. When 0, no effect RW 0 5:4 TSLOT_LENGTH Time slot duration programming (EEPROM bit): When 00: 0 µs When 01: 200 µs When 10: 500 µs When 11: 2 ms (Default value: See boot configuration) RW 0x3 3 SLEEPSIG_POL When 1, SLEEP signal active-high When 0, SLEEP signal active-low RW 0 2 PWON_LP_OFF When 1, allows device turnoff after a PWON Long Press (signal low) (EEPROM bits). (Default value: See boot configuration) RW 1 1 PWON_LP_RST When 1, allows digital core reset when the device is OFF (EEPROM bit). (Default value: See boot configuration) RW 0 0 IT_POL INT1 interrupt pad polarity control signal (EEPROM bit): When 0, active low When 1, active high (Default value: See boot configuration) RW 0 |
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