SWCS049G datasheet(96/144 Pages) TI

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TPS65911

SWCS049S – JUNE 2010 – REVISED AUGUST 2018

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Detailed Description

Table 6-58. SLEEP_KEEP_LDO_ON_REG

Address Offset

0x41

Instance

Reset Domain: GENERAL RESET

Description

When corresponding control bit = 0 in EN1_ LDO_ASS register (default setting): Configuration Register keeping the

full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.

When control bit = 1, LDO regulator full load capability (ACTIVE mode) is maintained during device SLEEP state.

When control bit = 0, the LDO regulator is set or stay in low-power mode during device SLEEP state(but then

supply state can be overwritten programming ST[1:0]). Control bit value has no effect if the LDO regulator is off.

When corresponding control bit = 1 in EN1_ LDO_ASS register: Configuration Register setting the LDO regulator

state driven by SCLSR_EN1 signal low level (when SCLSR_EN1 is high the regulator is on, full power):

- the regulator is set off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)

- the regulator is set in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register

Type

LDO3_

KEEPON

LDO4_

KEEPON

LDO7_KEEPO

LDO8_

KEEPON

LDO5_KEEPO

LDO2_

KEEPON

LDO1_

KEEPON

LDO6_

KEEPON

Bits

Field Name

Description

Type

Reset

LDO3_KEEPON