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AM6442...ALV 数据表(PDF) 60 Page - Texas Instruments |
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AM6442...ALV 数据表(HTML) 60 Page - Texas Instruments |
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60 / 244 page  Table 6-2. ADC0 Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALV PIN [4] ADC0_AIN7 (1) (2) (3) A ADC Analog Input 7 / GPIO1_87 (Input Only) E20 ADC_EXT_TRIGGER0 I ADC Trigger Input B16, C13 ADC_EXT_TRIGGER1 I ADC Trigger Input D14, D16 (1) The General Purpose Input signal associated with this ADC0_AIN input has a debounce function when ADC0 is configured to operate in GPI mode. For more information on configuring ADC0 to operate in GPI mode, see the TRM Analog-to-Digital Converter (ADC) section in the Peripherals chapter. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. (2) The ADC0_AIN[7:0] inputs only have hysterisis when ADC0 is configured to operate in GPI mode. (3) Any unused ADC0_AIN inputs must be pulled to VSS through a resistor or connected directly to VSS when VDDA_ADC is connected to a power source. (4) The ADC0_REFP and ADC0_REFN inputs are analog inputs which must be treated like high transient power supply rails, where ADC0_REFN is expected to be connected directly to the PCB ground plane and ADC0_REFP is connected to a 4mA power source with high frequency decoupling capacitors placed in the ball array on the back side of the PCB and connected directly to the ADC0_REFP and ADC0_REFN package balls with vias. 6.3.2 CPSW3G 6.3.2.1 MAIN Domain Table 6-3. CPSW3G0 RGMII1 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALV PIN [4] RGMII1_RXC I RGMII Receive Clock AA5, W13 RGMII1_RX_CTL I RGMII Receive Control V13, W6 RGMII1_TXC IO RGMII Transmit Clock U14 RGMII1_TX_CTL O RGMII Transmit Control U15 RGMII1_RD0 I RGMII Receive Data 0 AA13, W5 RGMII1_RD1 I RGMII Receive Data 1 U12, Y5 RGMII1_RD2 I RGMII Receive Data 2 V6, Y13 RGMII1_RD3 I RGMII Receive Data 3 V12, V5 RGMII1_TD0 O RGMII Transmit Data 0 V15 RGMII1_TD1 O RGMII Transmit Data 1 V14 RGMII1_TD2 O RGMII Transmit Data 2 W14 RGMII1_TD3 O RGMII Transmit Data 3 AA14 Table 6-4. CPSW3G0 RGMII2 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALV PIN [4] RGMII2_RXC I RGMII Receive Clock U11 RGMII2_RX_CTL I RGMII Receive Control W12 RGMII2_TXC IO RGMII Transmit Clock Y10 RGMII2_TX_CTL O RGMII Transmit Control Y11 RGMII2_RD0 I RGMII Receive Data 0 W11 RGMII2_RD1 I RGMII Receive Data 1 V11 RGMII2_RD2 I RGMII Receive Data 2 AA12 RGMII2_RD3 I RGMII Receive Data 3 Y12 RGMII2_TD0 O RGMII Transmit Data 0 AA10 RGMII2_TD1 O RGMII Transmit Data 1 V10 RGMII2_TD2 O RGMII Transmit Data 2 U10 RGMII2_TD3 O RGMII Transmit Data 3 AA11 AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 60 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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