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AM6442...ALV 数据表(PDF) 21 Page - Texas Instruments

部件名 AM6442...ALV
功能描述  AM64x Sitara™ Processors
PDF  244 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM6442...ALV 数据表(HTML) 21 Page - Texas Instruments

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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
N17
GPMC0_DIR
PADCONFIG:
PADCONFIG41
0x000F40A4
GPMC0_DIR
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
EQEP0_B
3
I
0
GPIO0_40
7
IO
pad
EHRPWM6_B
8
IO
0
PRG1_PWM2_B0
9
IO
1
R18
GPMC0_OEn_REn
PADCONFIG:
PADCONFIG34
0x000F4088
GPMC0_OEn_REn
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
FSI_RX5_D0
1
I
0
UART5_TXD
2
O
EHRPWM4_A
3
IO
0
TRC_DATA16
6
O
GPIO0_33
7
IO
pad
PRG0_PWM3_A1
9
IO
0
T21
GPMC0_WEn
PADCONFIG:
PADCONFIG35
0x000F408C
GPMC0_WEn
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
FSI_RX5_D1
1
I
0
UART5_RTSn
2
O
EHRPWM4_B
3
IO
0
TRC_DATA17
6
O
GPIO0_34
7
IO
pad
PRG0_PWM3_B1
9
IO
1
N16
GPMC0_WPn
PADCONFIG:
PADCONFIG40
0x000F40A0
GPMC0_WPn
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
FSI_TX1_CLK
1
O
EQEP0_A
3
I
0
GPMC0_A22
4
OZ
TRC_DATA22
6
O
GPIO0_39
7
IO
pad
EHRPWM6_A
8
IO
0
PRG1_PWM2_A0
9
IO
0
T20
GPMC0_AD0
PADCONFIG:
PADCONFIG15
0x000F403C
GPMC0_AD0
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
FSI_RX2_CLK
1
I
0
UART2_RXD
2
I
1
EHRPWM0_SYNCI
3
I
0
TRC_CLK
6
O
GPIO0_15
7
IO
pad
BOOTMODE00
Bootstrap
I
www.ti.com
AM6442, AM6441, AM6421, AM6412, AM6411
SPRSP56D – JANUARY 2021 – REVISED JULY 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411



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