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AM6442...ALV 数据表(PDF) 88 Page - Texas Instruments |
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AM6442...ALV 数据表(HTML) 88 Page - Texas Instruments |
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88 / 244 page  Table 6-60. PRU_ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALV PIN [4] PRG1_RGMII2_RD2 I PRU_ICSSG RGMII Receive Data AA12 PRG1_RGMII2_RD3 I PRU_ICSSG RGMII Receive Data Y12 PRG1_RGMII2_TD0 O PRU_ICSSG RGMII Transmit Data AA10 PRG1_RGMII2_TD1 O PRU_ICSSG RGMII Transmit Data V10 PRG1_RGMII2_TD2 O PRU_ICSSG RGMII Transmit Data U10 PRG1_RGMII2_TD3 O PRU_ICSSG RGMII Transmit Data AA11 PRG1_UART0_CTSn I PRU-ICSSG UART Clear to Send (active low) U15 PRG1_UART0_RTSn O PRU-ICSSG UART Request to Send (active low) U14 PRG1_UART0_RXD I PRU-ICSSG UART Receive Data V14 PRG1_UART0_TXD O PRU-ICSSG UART Transmit Data W14 6.3.20 Reserved Table 6-61. Reserved Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALV PIN [4] RSVD0 N/A Reserved, must be left unconnected H16 RSVD1 N/A Reserved, must be left unconnected D21 RSVD2 N/A Reserved, must be left unconnected G13 RSVD3 N/A Reserved, must be left unconnected F17 RSVD4 N/A Reserved, must be left unconnected W15 RSVD5 N/A Reserved, must be left unconnected V16 RSVD6 N/A Reserved, must be left unconnected K2 RSVD7 N/A Reserved, must be left unconnected K1 RSVD8 N/A Reserved, must be left unconnected F12 6.3.21 SERDES 6.3.21.1 MAIN Domain Table 6-62. SERDES0 Signal Descriptions SIGNAL NAME [1] ((2)) PIN TYPE [2] DESCRIPTION [3] ALV PIN [4] PCIE0_CLKREQn IO PCIE Clock Request Signal D16 SERDES0_REXT (1) A External Calibration Resistor T13 SERDES0_REFCLK0N IO Serdes Reference Clock Input/Output (negative) W16 SERDES0_REFCLK0P IO Serdes Reference Clock Input/Output (positive) W17 SERDES0_RX0_N I SERDES Differential Receive Data (negative) Y15 SERDES0_RX0_P I SERDES Differential Receive Data (positive) Y16 SERDES0_TX0_N O SERDES Differential Transmit Data (negative) AA16 SERDES0_TX0_P O SERDES Differential Transmit Data (positive) AA17 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) The functionality of these pins is controlled by SERDES0_LN0_CTRL_LANE_FUNC_SEL. 6.3.22 System and Miscellaneous 6.3.22.1 Boot Mode Configuration 6.3.22.1.1 MAIN Domain Table 6-63. Sysboot Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALV PIN [4] BOOTMODE00 I Bootmode pin 0 T20 BOOTMODE01 I Bootmode pin 1 U21 AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 88 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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