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AM6442...ALV 数据表(PDF) 135 Page - Texas Instruments |
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AM6442...ALV 数据表(HTML) 135 Page - Texas Instruments |
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135 / 244 page  B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC. Figure 7-27. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics - RGMII Mode 7.10.5.1.4 CPSW3G IOSETs Table 7-31 defines valid pin combinations of each CPSW3G MDIO0 IOSET. Table 7-31. CPSW3G MDIO0 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE MDIO0_MDIO PRG0_PRU1_GPO18 4 PRG1_MDIO0_MDIO 4 MDIO0_MDC PRG0_PRU1_GPO19 4 PRG1_MDIO0_MDC 4 Table 7-32 defines valid pin combinations of each CPSW3G RMII1 and RMII2 IOSET. Table 7-32. CPSW3G RMII1 and RMII2 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE RMII_REF_CLK(1) PRG1_PRU0_GPO10 5 PRG0_PRU0_GPO10 5 RMII1_CRS_DV PRG1_PRU1_GPO19 5 PRG0_PRU1_GPO19 5 RMII1_RX_ER PRG1_PRU0_GPO9 5 PRG0_PRU0_GPO9 5 RMII1_RXD0 PRG1_PRU1_GPO7 5 PRG0_PRU1_GPO7 5 RMII1_RXD1 PRG1_PRU1_GPO9 5 PRG0_PRU1_GPO9 5 RMII1_TXD0 PRG1_PRU1_GPO10 5 PRG0_PRU1_GPO10 5 RMII1_TXD1 PRG1_PRU1_GPO17 5 PRG0_PRU1_GPO17 5 RMII1_TX_EN PRG1_PRU1_GPO18 5 PRG0_PRU1_GPO18 5 RMII2_CRS_DV PRG1_PRU1_GPO13 5 PRG1_PRU1_GPO13 5 RMII2_RX_ER PRG1_PRU1_GPO4 5 PRG1_PRU1_GPO4 5 RMII2_RXD0 PRG1_PRU1_GPO0 5 PRG1_PRU1_GPO0 5 RMII2_RXD1 PRG1_PRU1_GPO1 5 PRG1_PRU1_GPO1 5 RMII2_TXD0 PRG1_PRU1_GPO11 5 PRG1_PRU1_GPO11 5 RMII2_TXD1 PRG1_PRU1_GPO12 5 PRG1_PRU1_GPO12 5 RMII2_TX_EN PRG1_PRU1_GPO15 5 PRG1_PRU1_GPO15 5 (1) RMII_REF_CLK is common to both RMII1 and RMII2. For proper operation, all pin multiplexed signal assignments must use the same IOSET. Table 7-33 defines valid pin combinations of each CPSW3G RGMII1 IOSET. Table 7-33. CPSW3G RGMII1 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE RGMII1_TX_CTL PRG1_PRU0_GPO9 4 PRG1_PRU0_GPO9 4 RGMII1_TXC PRG1_PRU0_GPO10 4 PRG1_PRU0_GPO10 4 RGMII1_TD0 PRG1_PRU1_GPO7 4 PRG1_PRU1_GPO7 4 RGMII1_TD1 PRG1_PRU1_GPO9 4 PRG1_PRU1_GPO9 4 RGMII1_TD2 PRG1_PRU1_GPO10 4 PRG1_PRU1_GPO10 4 RGMII1_TD3 PRG1_PRU1_GPO17 4 PRG1_PRU1_GPO17 4 RGMII1_RX_CTL PRG0_PRU0_GPO9 4 PRG1_PRU0_GPO5 4 RGMII1_RXC PRG0_PRU0_GPO10 4 PRG1_PRU0_GPO8 4 www.ti.com AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 135 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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