AM6442...ALV datasheet(214/244 Pages) TI

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8.2 Processor Subsystems

8.2.1 Arm Cortex-A53 Subsystem

The A53SS module supports the following features:

• Dual Core A53 Cluster

– Full ARM v8-A Architecture Compliant

• AArch32 and AArch64 Execution States

• All exception levels EL0-3

• A32 Instruction Set (Previously ARM instruction set)

• T32 instruction set (previously Thumb instruction set)

• A64 Instruction Set

– Advanced SIMD and Floating Point Extensions (NEON)

– ARMv8 Cryptography Extensions

– ARM GICv3 architecture

– In-order pipeline with symmetric dual-issue of most instructions

– Harvard L1 with system MMU

• 32 KB Instruction Cache

• 32 KB Data Cache

– 256KB Shared L2 Cache

– Generic Timer(s)

– Debug

• 128-Bit VBUSM Master Interfaces (for axi_r and axi_r channels)

• 128-Bit VBUSM Slave Interface (for Accelerator Coherency Port)

• 64-bit Grey-coded system input time

• 48-bit Grey-coded debug input time

• 32-bit VBUSP slave interface for Debug

• Integrated PBIST controller with BISOR

For more information, see Dual-A53 MPU Subsystem section in Processors and Accelerators chapter in the

device TRM.

8.2.2 Arm Cortex-R5F Subsystem (R5FSS)

The R5FSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for dual/single-core

operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®

CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and

various wrappers for protocol conversion and address translation for easy integration into the SoC.

Note

The Cortex®-R5F processor is a Cortex-R5 processor that includes the optional Floating Point Unit

(FPU) extension.

For more information, see Dual-R5F Subsystem (R5FSS) section in Processors and Accelerators chapter in the

device TRM.

8.2.3 Arm Cortex-M4F (M4FSS)

The M4FSS module on the AM64x device provides a safety channel (secondary channel - working in conjunction

with an external microcontroller)- or- a general purpose MCU.

The M4FSS module supports the following features:

• Cortex M4F With MPU

• ARMv7-M architecture

• Support for Nested Vectored Interrupt Controller (NVIC) with 64 inputs

• Ability to executed code from internal or external memories

• 192 KB of SRAM (I-Code)

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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