AM6442...ALV datasheet(220/244 Pages) TI

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– high-speed mode (up to 3.4Mb/s), I2C0 and MCU_I2C0 only

• Multi-master transmitter and slave receiver mode

• Multi-master receiver and slave transmitter mode

• Combined master transmit/receive and receive/transmit modes

• 7-bit and 10-bit device addressing modes

• Built-in 32 byte FIFO for buffered read or write

• Programmable multi-slave channel (responds to 4 separates addresses)

• Programmable clock generation

• Support for asynchronous wake-up

• One interrupt line

For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device

TRM.

8.4.2.12 MCAN

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed

real-time control with a high level of security. CAN has high immunity to electrical interference and the ability

to self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire

network, which provides for data consistency in every node of the system.

The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN

FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices

can coexist on the same network without any conflict.

The device supports 2 MCAN modules

For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device

TRM.

8.4.2.13 MCRC Controller

VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the

integrity of a memory system. A signature representing the contents of the memory is obtained when the

contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate

the signature for a set of data and then compare the calculated signature value against a pre-determined good

signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in

parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC

controller compresses each data being read through CPU read data bus.

For more information, see MCRC Controller section in Interprocessor Communication chapter in the device

TRM.

8.4.2.14 MCSPI

The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.

There are total of seven MCSPI modules in the device.

For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the

device TRM.

8.4.2.15 MMCSD

There are two Multi-Media Card/Secure Digital (MMCSD) modules inside the device - MMCSD0 and MMCSD1.

Each MMCSD module includes one MMCSD Host Controller, where MMCSD0 is associated with MMC0 and

MMCSD1 is associated with MMC1.

The MMCSD Host Controller supports:

• One controller with 8-bit wide data bus

• One controller with 4-bit wide data bus

• Support of eMMC5.1 Host Specification (JESD84-B51)

• Support of SD Host Controller Standard Specification - SDIO 3.00

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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