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Table 7-47. FSI Switching Characteristics - SPI Mode (continued)

see Figure 7-38

NO.

PARAMETER

MODE

MIN

MAX

UNIT

FSIT8 td(TX_CLK-TX_D1)

Delay time, FSI_TXn_CLK low to FSI_TXn_D1 high

SPI Mode

P - 2

(1)

P = FSI_TXn_CLK period in ns.

FSI_TXn_CLK

FSIT5

FSIT4

FSI_TXn_D0

FSI_TXn_D1

FSIT6

FSIT7

FSIT8

FSIT5

Figure 7-38. FSI Switching Characteristics - SPI Mode

For more information, see Fast Serial Interface section in Peripherals chapter in the device TRM.

7.10.5.7 GPIO

Table 7-48, Table 7-49, and Table 7-50 present timing conditions, requirements, and switching characteristics for

GPIO.

For more details about features and additional description information on the device GPIO, see the

corresponding subsections within Signal Descriptions and Detailed Description sections.

Note

The device has multiple GPIO modules. GPIOn_x is generic name used to describe a GPIO signal,

where n represents the specific GPIO module and x represents one of the input/output signals

associated with the module.

Table 7-48. GPIO Timing Conditions

PARAMETER

BUFFER TYPE

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

LVCMOS

0.75

6.6

V/ns

I2C OD FS

TBD

V/ns

OUTPUT CONDITIONS

Output load capacitance

LVCMOS

I2C OD FS

100

Table 7-49. GPIO Timing Requirements

NO.

PARAMETER

DESCRIPTION

BUFFER TYPE

MIN

MAX

UNIT

GPIO1 tw(GPIO_IN)

Pulse width, GPIOn_x

LVCMOS

2P + 2.6

(1)

I2C OD FS

2P + 2.6

(1)

P = functional clock period in ns.

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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