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Table 7-101. OSPI0 Timing Requirements – PHY DDR Mode

see Figure 7-85

NO.

MODE

MIN

MAX

UNIT

O15

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

1.8V, DDR with External Board Loopback

0.53

1.8V, DDR with DQS

-0.46

3.3V, DDR with External Board Loopback

1.23

3.3V, DDR with DQS

-0.66

O16

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

1.8V, DDR with External Board Loopback

1.24(1)

1.8V, DDR with DQS

3.59

3.3V, DDR with External Board Loopback

1.44(1)

3.3V, DDR with DQS

7.92

(1)

This Hold time requirement is larger than the Hold time provided by a typical OSPI/QSPI/SPI device. Therefore, the trace length

between the SoC and attached OSPI/QSPI/SPI device must be sufficiently long enough to ensure that the Hold time is met at the SoC.

The length of the SoC's external loopback clock (OSPI0_LBCLKO to OSPI0_DQS) may need to be shortened to compensate.

OSPI_DQS

O16

O15

OSPI_TIMING_04

OSPI_D[i:0]

O16

O15

Figure 7-85. OSPI0 Timing Requirements – PHY DDR with External Board Loopback or DQS

Table 7-102. OSPI0 Switching Characteristics – PHY DDR Mode

see Figure 7-86

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

tw(CLKL)

Pulse duration, OSPI0_CLK low

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

((0.475P(1)) - 0.3)

td(CLK-CSn)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

((0.475P(1)) -

(0.975M(2)R(4)))

((0.525P(1)) -

(1.025M(2)R(4)) + 7)

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

((0.475P(1)) +

(0.975N(3)R(4)) - 7)

((0.525P(1)) +

(1.025N(3)R(4)))

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

1.8V

-7.71

-1.56

3.3V

-7.71

-1.56

(1)

P = OSPI0_CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = refclk cycle time in ns

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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