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AM6421...ALV 数据表(PDF) 168 Page - Texas Instruments |
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AM6421...ALV 数据表(HTML) 168 Page - Texas Instruments |
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168 / 244 page  Table 7-60. MCAN Timing Conditions (continued) PARAMETER MIN MAX UNIT SRI Input slew rate 2 15 V/ns OUTPUT CONDITIONS CL Output load capacitance 5 20 pF Table 7-61. MCAN Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT MCAN1 td(MCAN_TX) Delay time, transmit shift register to MCANn_TX 10 ns MCAN2 td(MCAN_RX) Delay time, MCANn_RX to receive shift register 10 ns For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM. 7.10.5.11 MCSPI For more details about features and additional description information on the device Serial Port Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 7-62 presents timing conditions for MCSPI. For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the device TRM. Table 7-62. MCSPI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2 8.5 V/ns OUTPUT CONDITIONS CL Output load capacitance 6 12 pF 7.10.5.11.1 MCSPI — Master Mode Table 7-63, Figure 7-55, Table 7-64, and Figure 7-56 present timing requirements and switching characteristics for SPI – Master Mode. Table 7-63. MCSPI Timing Requirements – Master Mode see Figure 7-55 NO. PARAMETER DESCRIPTION MIN MAX UNIT SM4 tsu(MISO-SPICLK) Setup time, SPIn_D[x] valid before SPIn_CLK active edge 2.8 ns SM5 th(SPICLK-MISO) Hold time, SPIn_D[x] valid after SPIn_CLK active edge 3 ns AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 168 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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