AM6421...ALV datasheet(170/244 Pages) TI

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(3)

B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (OUT)

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (OUT)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit0

PHA=0

EPOL=1

POL=0

POL=1

PHA=1

EPOL=1

POL=0

POL=1

SM8

SM9

SM6

SM3

SM1

SM2

SM1

SM8

SM9

SM3

SM1

SM2

SM1

SM6

SM7

SM6

SM2

SM3

SM2

SM3

SM6

SPRSP08_TIMING_McSPI_01

Figure 7-56. SPI Master Mode Transmit Timing

7.10.5.11.2 MCSPI — Slave Mode

Table 7-65, Figure 7-57, Table 7-66, and Figure 7-58 present timing requirements and switching characteristics

for SPI – Slave Mode.

Table 7-65. MCSPI Timing Requirements – Slave Mode

see Figure 7-57

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SS1

tc(SPICLK)

Cycle time, SPIn_CLK

SS2

tw(SPICLKL)

Pulse duration, SPIn_CLK low

0.45P

(1)

SS3

tw(SPICLKH)

Pulse duration, SPIn_CLK high

0.45P

(1)

SS4

tsu(SIMO-SPICLK)

Setup time, SPIn_D[x] valid before SPIn_CLK active edge

SS5

th(SPICLK-SIMO)

Hold time, SPIn_D[x] valid after SPIn_CLK active edge

SS8

tsu(CS-SPICLK)

Setup time, SPIn_CSi valid before SPIn_CLK first edge

SS9

th(SPICLK-CS)

Hold time, SPIn_CSi valid after SPIn_CLK last edge

(1)

P = SPIn_CLK period in ns.

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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