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AM6421...ALV 数据表(PDF) 169 Page - Texas Instruments |
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AM6421...ALV 数据表(HTML) 169 Page - Texas Instruments |
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169 / 244 page  SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (IN) SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 PHA=1 EPOL=1 POL=0 POL=1 POL=0 POL=1 SM8 SM9 SM3 SM1 SM2 SM1 SM8 SM9 SM3 SM1 SM2 SM1 SM2 SM3 SM2 SM3 SM4 SM5 SM4 SM5 SM4 SM4 SM5 SM5 SPRSP08_TIMING_McSPI_02 Figure 7-55. SPI Master Mode Receive Timing Table 7-64. MCSPI Switching Characteristics - Master Mode see Figure 7-56 NO. PARAMETER MIN MAX UNIT SM1 tc(SPICLK) Cycle time, SPIn_CLK 20 ns SM2 tw(SPICLKL) Pulse duration, SPIn_CLK low 0.5P - 1 (1) ns SM3 tw(SPICLKH) Pulse duration, SPIn_CLK high 0.5P - 1 (1) ns SM6 td(SPICLK-SIMO) Delay time, SPIn_CLK active edge to SPIn_D[x] -3 2.5 ns SM7 td(CS-SIMO) Delay time, SPIn_CSi active edge to SPIn_D[x] 5 ns SM8 td(CS-SPICLK) Delay time, SPIn_CSi active to SPIn_CLK first edge PHA = 0 B - 4 (3) ns PHA = 1 A - 4 (2) ns SM9 td(SPICLK-CS) Delay time, SPIn_CLK last edge to SPIn_CSi inactive PHA = 0 A - 4 (2) ns PHA = 1 B - 4 (3) ns (1) P = SPI_CLK period in ns. (2) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. www.ti.com AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 169 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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