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AM6411...ALV 数据表(PDF) 208 Page - Texas Instruments |
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AM6411...ALV 数据表(HTML) 208 Page - Texas Instruments |
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208 / 244 page  Table 7-139. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TXC (continued) see Figure 7-113 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII7 tw(TXCH) Pulse duration, RGMII[x]_TXC high 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns RGMII8 tw(TXCL) Pulse duration, RGMII[x]_TXC low 10 Mbps 160 240 ns 100 Mbps 16 24 ns 1000 Mbps 3.6 4.4 ns Table 7-140. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL see Figure 7-113 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII9 tosu(TD-TXC) Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC high/low 10 Mbps 1.2 ns 100 Mbps 1.2 ns 1000 Mbps 1.2 ns tosu(TX_CTL-TXC) Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC high/low 10 Mbps 1.2 ns 100 Mbps 1.2 ns 1000 Mbps 1.2 ns RGMII10 toh(TXC-TD) Output setup time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC high/low 10 Mbps 1.2 ns 100 Mbps 1.2 ns 1000 Mbps 1.2 ns toh(TXC-TX_CTL) Output setup time, RGMII[x]_TX_CTL valid after RGMII[x]_TXC high/low 10 Mbps 1.2 ns 100 Mbps 1.2 ns 1000 Mbps 1.2 ns RGMII[x]_TXC (A) RGMII[x]_TD[3:0] (B) RGMII[x] TX_CTL _ (B) RGMII9 1st Half-byte TXERR TXEN 2nd Half-byte RGMII7 RGMII8 RGMII6 RGMII10 A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC. Figure 7-113. PRU_ICSSG RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics - RGMII Mode 7.10.5.17 Timers For more details about features and additional description information on the device Timers, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 7-141. Timer Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 208 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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