Functional description of the SPI

L99MOD51XP

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DS12667 Rev 6

5

Functional description of the SPI

5.1

Serial Peripheral Interface (SPI)

This device uses a standard SPI to communicate with a microcontroller. The SPI can be

driven by a microcontroller with its SPI peripheral running in the following mode: CPOL = 0

and CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and

output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible

output pins and one input pin will be needed to communicate with the device. A fault

condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the

status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers

0 and 1. The microcontroller can poll the status of the device without the need of a full SPI-

communication cycle.

Note:

In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see

Figure 3).

5.2

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the

output pin (DO) will be in high impedance state. A low signal will activate the output driver

and a serial communication can be started.

The state when CSN is going low until the rising edge of CSN will be called a

communication frame.

Note:

The device includes a test mode. This mode is activated by a dedicated sequence which

includes a high voltage at the CSN Pin. The CSN Pin must be kept at nominal voltage levels

in order to avoid accidental activation of the test mode.

5.3

Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be

sampled at the rising edge of the CLK signal and shifted into an internal 16-bit shift register.

At the rising edge of the CSN signal the contents of the shift register will be transferred to

Data Input Register.

The writing to the selected Data Input Register is only enabled if exactly 16 bits are

transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are

counted within one frame the complete frame will be ignored. This safety function is

implemented to avoid an activation of the output stages by a wrong communication frame.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is

recommended.