L99MOD53XP datasheet(7/35 Pages) STMICROELECTRONICS

7 / 35 page

DS12617 Rev 5

7/35

L99MOD53XP

Block diagram and pin description

Figure 2. Configuration diagram (top view)

OUT4

GND 1

OUT8 2

OUT1 3

CM / PWM2

Vcc

OUT4

GND

OUT6

OUT8

PWM1

OUT5

GND

OUT7

OUT3

OUT2

CSN

GND

CLK

PowerSSO-36

Table 2. Pin definitions and functions

Symbol

Function

1, 18, 19, 36

GND

Ground:

reference potential.



Important: for the capability of driving the full current at the outputs all pins of

GND must be externally connected.

2, 35

OUT8

High-side-driver-output 8

The output is built by a high-side switch and is intended for resistive loads, hence

the internal reverse diode from GND to the output is missing. For ESD reason a

diode to GND is present but the energy which can be dissipated is limited. The

high-side driver is a power DMOS transistor with an internal parasitic reverse

diode from the output to VS (bulk-drain-diode). The output is over-current and

open-load protected.



Important: for the capability of driving the full current at the outputs both pins of

OUT8 must be externally connected.

OUT1 OUT2

OUT3

Half-bridge-output 1,2,3

The output is built by a high-side and a low-side switch, which are internally

connected. The output stage of both switches is a power DMOS transistor. Each

driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver

from output to VS, low-side driver from GND to output). This output is over-

current and open-load protected.

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