Functional description of the SPI

L99MOD53XP

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DS12617 Rev 5

content of the selected status register into the data out shift register. Each subsequent

falling edge of the CLK shift the next bit out.

4.5

Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the

falling edge of the CLK signal.

4.6

Input data register

The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of

the two Input Registers. All bits are first shifted into an input shift register. After the rising

edge of CSN the contents of the input shift register are written to the selected Input Data

Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the content of

the selected status register is transferred to DO during the current communication frame. Bit

1-17 controls the behavior of the corresponding driver.

If bit 23 is zero, the device goes into the standby-mode. The bits 18 and 19 are used to

control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status

registers. The bits in the status registers are cleared after the current communication frame

(rising edge of CSN).

4.7

Status register

This device uses two status registers to store and to monitor the state of the device. Bit 0 is

used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The

state of this bit can be polled by the microcontroller without the need of a full SPI

communication cycle. If one of the over-current bits is set, the corresponding driver is

disabled. If the over-current recovery bit of the output is not set the microcontroller has to

clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers go

into a high impedance state. Again the microcontroller has to clear the bit to enable the

drivers.