L99MOD53XP datasheet(8/35 Pages) STMICROELECTRONICS

8 / 35 page

Block diagram and pin description

L99MOD53XP

8/35

DS12617 Rev 5

6, 7, 14, 15, 23,

25, 28, 32

Power supply voltage (external reverse protection required)

For this input a ceramic capacitor as close as possible to GND is recommended.

Important: for the capability of driving the full current at the outputs all pins of VS

must be externally connected.

8DI

Serial data input

The input requires CMOS logic levels and receives serial data from the

microcontroller. The data is a 24bit control word and the least significant bit (LSB,

bit 0) is transferred first.

CM/PWM2

Current monitor output/PWM2 input

Depending on the selected multiplexer bits of input data register this output

sources an image of the instant current through the corresponding high-side

driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can

overdrive the current monitor signal to provide a second PWM input for the output

OUT7.

CSN

Chip select not input

This input is low active and requires CMOS logic levels. The serial data transfer

between L99MOD53XP and micro controller is enabled by pulling the input CSN

to low level.

Serial data output

The diagnosis data is available via the SPI and this 3-state output. The output will

remain in 3-state, if the chip is not selected by the input CSN (CSN = high)

VCC

Logic supply voltage

For this input a ceramic capacitor as close as possible to GND is recommended.

CLK

Serial clock input

This input controls the internal shift register of the SPI and requires CMOS logic

levels.

16, 17, 20, 21

OUT4 OUT5

Half-bridge-output 4,5:

see OUT1 (pin 3).

Important: for the capability of driving the full current at the outputs both pins of

OUT4 (OUT5, respectively) must be externally connected.

Charge pump output

This output is provided to drive the gate of an external n-channel PowerMOS

used for reverse polarity protection

PWM1

PWM1 input:

This input signal can be used to control the drivers OUT1-OUT6 and OUT8 by an

external PWM signal.

OUT6,

OUT7

High side-driver-output 6,7:

Each output is built by a high-side switch and is intended for resistive loads,

hence the internal reverse diode from GND to the output is missing. For ESD

reason a diode to GND is present but the energy which can be dissipated is

limited. Each high-side driver is a power DMOS transistor with an internal

parasitic reverse diode from each output to VS (bulk-drain-diode). Each output is

over-current and open-load protected.

22, 24, 29,

30, 34

Not connected pins.

Table 2. Pin definitions and functions (continued)

Symbol

Function

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