List of figures

Figure 1.

Block diagram .................................................................... 2

Figure 2.

Pin connection (top view) ............................................................. 3

Figure 3.

Typical application circuit ............................................................. 4

Figure 4.

Typical application circuit with reverse current protection ....................................... 4

Figure 5.

Typical startup sequence for STELPD01 and STELPD01A ...................................... 8

Figure 6.

Delay time and VOUT ramp-up time ...................................................... 9

Figure 7.

EN/Fault driver circuit .............................................................. 11

Figure 8.

External gate driver circuit ........................................................... 12

Figure 9.

ILIM vs. RLIM ..................................................................... 13

Figure 10.

ILIM vs. RLIM (magnification) .......................................................... 13

Figure 11.

Bias current vs. temperature (ON Mode) ................................................. 13

Figure 12.

Bias current vs. temperature (Fault Mode) ................................................ 13

Figure 13.

Bias current vs. temperature (OFF Mode) ................................................ 14

Figure 14.

RDS_ON vs. temperature............................................................. 14

Figure 15.

ILIM vs. temperature ............................................................... 14

Figure 16.

Clamping voltage vs. temperature ...................................................... 14

Figure 17.

UVLO vs. temperature .............................................................. 14

Figure 18.

UVLO Hysteresis vs. temperature ...................................................... 14

Figure 19.

EN/Fault pin thresholds vs. temperature.................................................. 15

Figure 20.

EN/Fault pull-up voltage vs. temperature ................................................. 15

Figure 21.

EN/Fault pin current vs. temperature (EN/Fault to GND)....................................... 15

Figure 22.

Soft-start time vs. temperature (no Cdv/dt) ................................................ 15

Figure 23.

External FET clamp voltage (VFETmax) vs. input voltage ....................................... 15

Figure 24.

Startup with no load ............................................................... 15

Figure 25.

Startup with RLOAD = 5 Ω ............................................................ 16

Figure 26.

Startup into voltage clamp ........................................................... 16

Figure 27.

Voltage clamp during operation........................................................ 16

Figure 28.

Start-up into output short-circuit ....................................................... 16

Figure 29.

Startup into overload ............................................................... 16

Figure 30.

Overcurrent protection during operation (latched version)...................................... 16

Figure 31.

Output short-circuit during operation (latched version) ........................................ 17

Figure 32.

Power loss protection through UVLO .................................................... 17

Figure 33.

Power loss protection through EN/Fault .................................................. 17

Figure 34.

DFN10L (3x3 mm) package outline ..................................................... 18

Figure 35.

DFN10L (3x3 mm) recommended footprint ................................................ 19

Figure 36.

DFN10 (3 x 3 mm) reel drawing outline .................................................. 20

Figure 37.

DFN10 (3 x 3 mm) carrier tape ........................................................ 21

Figure 38.

DFN10 (3 x 3 mm) device orientation in tape .............................................. 21

STELPD01

List of figures

DS13254 - Rev 1

page 26/27