LSM6DSRX datasheet(49/171 Pages) STMICROELECTRONICS

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9.10

COUNTER_BDR_REG1 (0Bh)

Counter batch data rate register 1 (r/w)

Table 39. COUNTER_BDR_REG1 register

dataready_

pulsed

RST_

COUNTER_BDR

TRIG_

COUNTER_BDR

0(1)

CNT_BDR_

TH_10

CNT_BDR_

TH_9

CNT_BDR_

TH_8

1. This bit must be set to '0' for the correct operation of the device.

Table 40. COUNTER_BDR_REG1 register description

dataready_pulsed

Enables pulsed data-ready mode

(0: Data-ready latched mode (returns to 0 only after an interface reading) (default);

1: Data-ready pulsed mode (the data ready pulses are 75 µs long)

RST_COUNTER_BDR

Resets the internal counter of batch events for a single sensor.

This bit is automatically reset to zero if it was set to ‘1’.

TRIG_COUNTER_BDR

Selects the trigger for the internal counter of batch events between XL and gyro.

(0: XL batch event;

1: GYRO batch event)

CNT_BDR_TH_[10:8]

In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the

internal counter of batch events. When this counter reaches the threshold, the counter is reset and

the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.

9.11

COUNTER_BDR_REG2 (0Ch)

Counter batch data rate register 2 (r/w)

Table 41. COUNTER_BDR_REG2 register

CNT_BDR_

TH_7

CNT_BDR_

TH_6

CNT_BDR_

TH_5

CNT_BDR_

TH_4

CNT_BDR_

TH_3

CNT_BDR_

TH_2

CNT_BDR_

TH_1

CNT_BDR_

TH_0

Table 42. COUNTER_BDR_REG2 register description

CNT_BDR_TH_[7:0]

In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the

internal counter of batch events. When this counter reaches the threshold, the counter is reset and the

COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.

LSM6DSRX

COUNTER_BDR_REG1 (0Bh)

DS13007 - Rev 3

page 49/171

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