KTB8331

December 2021

– Revision 04b

Page 14 of 25

Kinetic Confidential

Thermal Shutdown Over-Temperature (OT)

Over-temperature (OT) protection occurs if the die junction temperature exceeds the thermal shutdown threshold

(TJ_SHDN). During thermal shutdown, the buck pauses all switching until the die temperature cools. Once cooled,

the buck re-starts with the programmed soft-start ramp.

The OT status is reflected in the MONITOR register and, if unmasked, latched into the INTLATCH register.

Trim Options

The KTB8331 is factory trimmed using one-time programmable (OTP) registers. Standard versions are available

for various default output voltage settings and modes

– see the Ordering Information section. Contact a Kinetic

Technologies representative regarding versions with other default settings or I2C slave addresses.

I2C Interface Description

I2C Serial Data Bus

The KTB8331 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter,

and a device receiving data as a receiver. The device that controls the bus is called a master, whereas the

devices controlled by the master are known as slaves. A master device must generate the serial clock (SCL),

control bus access and generate START and STOP conditions to control the bus. The KTB8331 operates as a

slave on the I2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast

mode (400kHz maximum clock rate) are defined. The KTB8331 works in both modes. Connections to the bus are

made through the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined in Figure 2:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data

line while the clock line is high are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy

Both data and clock lines remain HIGH.

Start Data Transfer

A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.

Stop Data Transfer

A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP

condition.

Data Valid

The state of the data line represents valid data when, after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of

the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions are not limited, and are determined by the master

device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit.

Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte.

The master device must generate an extra clock pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that

the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Setup and hold times

must also be taken into account.