KTB8331

December 2021

– Revision 04b

Page 24 of 25

Kinetic Confidential

Recommended PCB Layout

Refer to Figure 6 for two example PCB layouts optimized for small footprint, low EMI, and good performance.

One example fits in a narrow rectangular area, while the other example is nearly square. Both examples follow

the below PCB layout recommendations:

1.

Connect the input capacitor CIN as close as possible to the VIN and PGND pins using top-side thick metal

traces.

2.

Connect the ground terminals of output capacitors COUT as close as possible to the ground terminal of CIN

and the PGND pins using top-side metal.

3.

Connect the local top-side PGND island to the PCB ground plane using multiple parallel vias.

4.

Do not connect the AGND pins directly to the top-side PGND. Instead, connect the AGND pins to the

PCB ground plane using their own vias.

5.

Connect the inductor to the LX pins with a wide trace. For smallest CIN, the LX trace will not fit between

the top-side landing pads of a 1005M (0402) size capacitor. Therefore, the LX trace is normally routed on

PCB layer 2 or layer 3 using multiple parallel vias.

a.

The added inductance of vias in series with the actual inductor have minimal effect on

performance. However, it is important to use enough parallel vias to handle the peak inductor

current in the application.

b.

If using a larger CIN of 1608M (0603) size or more, it is possible to squeeze the LX route on the

top-side between the CIN landing pads. If pinched, make sure to widen the LX trace as much as

possible before and after the pinched area.

6.

Connect the VOUT terminals of the inductor to the output capacitors with a wide and short trace.

7.

Route the VOUT sense trace from COUT to the VOUT pin with care to keep it away from noisy traces,

especially the LX trace. Additionally, use ground fill to shield noise from coupling into the VOUT sense.

8.

Depending upon PCB design rules, it may be possible to place filled micro-vias directly under WLCSP

bumps. If not, route short traces to nearby vias.

Figure 6. Two recommended PCB layouts