KTB8331

December 2021

– Revision 04b

Page 20 of 25

Kinetic Confidential

MONITOR Status Register

Register Address 0x05

Bit

Name

Access

Default

Reset

Description

7

POK_STAT

R

0

VOUT Power OK Status

0 = VOUT is below POK comparator threshold

1 = VOUT is above POK comparator threshold

During normal operation, the POK_STAT bit is 1. During disabled,

soft-start or overload conditions, the POK_STAT bit is 0.

6

UVLO_STAT

R

0

VIN Under-Voltage Status

0 = VIN is above the UVLO comparator threshold

1 = VIN is below the UVLO comparator threshold

During normal operation or when disabled, the UVLO_STAT bit is

0. During low input voltage conditions, the buck is disabled by the

UVLO comparator and the UVLO_STAT bit is set to 1 (so long as

VIN remains above VPOR=1.8V).

5

OVP_STAT

R

0

VIN Over-Voltage Status

0 = VIN is below the OVP comparator threshold

1 = VIN is above the OVP comparator threshold

During normal operation or when disabled, the OVP_STAT bit is 0.

During high input voltage conditions, the buck is disabled by the

OVP comparator and the OVP_STAT bit is set to 1.

4

POS_STAT

R

0

VOUT Positive Slew Status

0 = VOUT is at its set value

1 = VOUT is slewing in the positive direction towards it set value

During normal operation, the POS_STAT bit is 0. During soft-start

or positive DVS slew transitions, the POS_STAT bit is 1.

3

NEG_STAT

R

0

VOUT Negative Slew Status

0 = VOUT is at its set value

1 = VOUT is slewing in the negative direction towards it set value

During normal operation, the NEG_STAT bit is 0. During negative

DVS slew transitions, the NEG_STAT bit is 1.

2

RESET_STAT

R/C

0

Software Reset Status Latch

0 = software reset was not performed since this bit was cleared

1 = software reset was performed since this bit was cleared

The RESET_STAT bit is set to 1 when a software reset is written to

the RESET bit (B2) in the CONTROL register. The RESET_STAT

bit is NOT reset by the software reset. Instead, it is cleared (reset

to 0) after the RESET_STAT bit is read or whenever chip power is

removed (VIN<VPOR).

1

OT_STAT

R

0

Over-Temperature Status

0 = the die is not in thermal shutdown

1 = the die is in thermal shutdown

During normal operation, the OT_STAT bit is 0. During thermal

shutdown, the OT_STAT bit is 1.

0

EN_STAT

R

0

Enable Status

0 = the buck is disabled by hardware or software

1 = the buck is enabled by hardware or software

During normal operation, the EN_STAT bit is 1. During hardware

or software disabled conditions, the EN_STAT bit is 0.