LT8686SJVPBF datasheet(20/26 Pages) AD

20 / 26 page

LT8686S

Rev. 0

For more information www.analog.com

PCB LAYOUT

The LT8686S is specifically designed to minimize EMI/

EMC emissions and to maximize efficiency when switch-

ing at high frequencies.

For proper operation and minimum EMI, care must be

taken during printed circuit board layout. A recommended

board layout is available with the latest LT8686S demo

board. Some general guidelines are available in the

remainder of this section.

Place a local, unbroken ground plane under the application

circuit on the layer closest to the surface layer and con-

nect the exposed GND pad to this layer. The exposed pad

ground connection should be made with the maximum

number of vias possible to reduce thermal and electrical

impedance to the board ground. For best performance,

maximize unbroken board ground planes in the vicinity

of the LT8686S.

The SW and BST nodes should be made as small as

possible to minimize noise coupling to sensitive traces.

Minimize traces connecting to the RT and all FB pins and

provide ground shielding as needed to minimize noise

coupling to these sensitive nodes.

For each buck regulator, place input bypass capaci-

tors close to the VINx pins with a low impedance con-

nection to the exposed pad through the ground plane

mentioned above.

The recommended layer use for a 4-layer board is:

• Layer 1 (Components): use 2oz (70µm) copper.

Unbroken high frequency/high current routing,

including SW and BST node routing, plus inductor,

input, and output capacitor placement. Ground fill on

the remainder.

• Layer 2 (Internal): Unbroken ground plane.

APPLICATIONS INFORMATION

• Layer 3 (Internal): Signal routing with ground plane

on remainder.

• Layer 4 (Bottom): Use 2oz (70µm) copper. Use

for remaining signal routing with ground fill on

the remainder.

THERMAL CONSIDERATIONS

The exposed pad is the path for conducting heat from

the silicon die to the PC board and the surrounding air.

For good heat conduction, thermal vias should be placed

under the device to conduct heat down to internal ground

planes and the back side of the board. Multiple small vias

work better than a few large ones as the copper plating of

the via is a much better conductor than the solder which

may or may not fill the via volume. The planes will dis-

tribute heat over a large area.

Power dissipated within the LT8686S will result in a junc-

tion temperature rise beyond the ambient temperature in

proportion to the package thermal resistance, θJA (°C/W).

The power dissipation within the LT8686S can be esti-

mated from an efficiency measurement by calculating the

total power loss, then subtracting power loss in compo-

nents external to the LT8686S, such as inductor DCR loss.

The maximum operating junction temperature is then esti-

mated by multiplying the estimated LT8686S power loss

by the package θJA and summing the result with the

maximum application ambient temperature.

A good board design can achieve a θJA of 20°C/W. If the

calculation of maximum junction temperature indicates

the LT8686S will operate near or above the allowed junc-

tion temperature, more precise thermal modeling may be

required, or design changes must be made to reduce the

die junction temperature. Design changes may include

reducing VVINx, reducing fSW, or reducing the operating

load current. Load current reduction may be achieved with

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