ST7294 datasheet(25/69 Pages) STMICROELECTRONICS

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ST7294

4.3 16-BIT TIMER

4.3.1 Introduction

The 16-bit programmable timer consists of a 16-bit

free running counter driven by a mask option con-

figurable prescaler and control logic for one input

capture and two output compare registers. It can

be used for many purposes including pulse length

measurement of one input signal and generation

of one output waveform.

Because the timer has a 16-bit architecture, each

of its specific function block is represented by two

registers. These registers contain the high order

byte and low order byte of that function. However

an access to the high order byte inhibits that spe-

cific timer capability until the low order byte is also

accessed.

Note that correct software procedures should set

the I bit of the Condition Code Register before ac-

cessing the high order byte to prevent an interrupt

from occurring between the accesses to the high

and low order bytes of any register.

The timer block diagram is shown on Figure 18.

4.3.2 Functional Description

4.3.2.1 Counter

The key element of the programmable timer is a

16-bit free running counter or counter register. It is

preceded by a prescaler which divides the internal

clock by four. This counter is incrementing by

each event.

Software can read the counter at any time without

affecting its value. It can be read from two loca-

tions, the Counter Register (0018h, 0019h) and

Alternate Counter Register (001Ah, 001Bh). The

only difference between these two read-only reg-

isters is the way the overflow flag TOF is handled

during a read sequence.

A read sequence containing only a read of the

least significant byte of the free running counter

(from either the Counter Register or the Alternate

Counter Register) will receive the LSB of the count

value at the time of the read. A read of the most

significant byte (from either the Counter Register

or the Alternate Counter Register) simultaneously

returns the MSB of the count value and causes the

LSB to be transferred into a buffer.

The buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MSB several times. The read se-

quence is completed by reading the free running

counter LSB, which actually returns the buffered

value.

As shown on Figure 20 and Figure 21, the free

running counter is configured to FFFCh during re-

set. During a Power-On Reset (POR), the counter

is also configured to FFFCh and begins running

after the oscillator start-up delay.

When the counter rolls over from FFFFh to 0000h,

the Timer Overflow flag (TOF) of the Timer Status

erated if the TOIE enable bit of the Timer Control

is cleared. If one of these conditions is false, the

interrupt remains pending to be issued as soon as

they are both true. The Interrupt Request is

cleared by reading TSR, while TOF is set followed

by an access (read or write) to the LSB of the

Counter Register.

The TOF flag is not affected by accesses to the Al-

ternate Counter Register. This feature allows si-

multaneous use of the overflow function and reads

of the free running counter at random times (for

example, to measure on elapsed time) without

risking to clear the TOF flag erroneously. Access-

es to the Timer without the intention of servicing

the TOF flag should therefore be performed to the

Alternate Counter Register while only the TOF

service routine accesses the Counter Register.

The free running counter can be reset under soft-

ware control. This is performed by writing to the

LSB of either the Counter Register or the Alternate

Counter Register. The counter and the prescaler

are then configured to their reset conditions. This

reset also completes any 16-bit access sequence.

All flags and enable bits are unchanged.

The value in the counter registers repeats every

262,144 internal processor clock cycles. As

shown on Figure 20, the counter increment is trig-

gered by a falling edge of the CPU clock.

The timer is not affected by the WAIT mode. In the

HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from pre-

vious count (MCU awoken by an interrupt) or from

reset count (MCU awoken by a reset).

4.3.2.2 Input Capture

The ST7294 features an Input Capture register

and an Input Capture interrupt enable bit. The 16-

bit Input Capture Register, ICR1, is made up of

two 8-bit registers: the most significant byte regis-

ter, ICHR1, located at 014h, and the least signifi-

cant byte register (ICLR1) located at 015h. The

read-only register ICR1 is used to latch the value

of the free running counter after a defined transi-

tion is sensed by the input capture edge detector

on ICAP. This transition is software programmable

through the IEDG1 bit of the Timer Control Regis-

ter. When IEDG1 is set, a rising edge triggers the

capture; when IEDG1 is low, the capture is trig-

gered by a falling edge.

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