ST7294 datasheet(28/69 Pages) STMICROELECTRONICS

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ST7294

After a processor write cycle to the OCHR1 regis-

ter, the output compare function is inhibited until

the OCLR1 is also written. Thus, the user must

write both bytes if the MSB is written first. A write

made to only the LSB will not inhibit the compare

function. The minimum time between two succes-

sive edges on the OCMP1 pin is a function of the

software program.

The OCMP1 output latch is forced low during reset

and stays low until valid compares change it to a

high level. Because the OCF1 flag and the OCR1

are indeterminate at power-on and are not affect-

ed by an external reset, care must be exercise

when initiating the output compare function with

software. The following procedure is recommend-

ed to prevent the OCF1 flag from being set be-

tween the time it is read and the write to OCR1:

Write to OCHR1 (further compares are inhibited).

Read the TSR (first step of the clearance of OCF1

[it may be already set]).

Write to OCLR1 (enables the output compare

function and clears OCF1).

4.3.2.6 Output Compare Register 2

The Output Compare Register 2 (OCR2) is a 16-

bit register, which is made up of two 8-bit regis-

ters: the most significant byte register (OCHR2) at

address 001Eh and the least significant byte reg-

ister (OCLR2) at address 001Fh.This register

works as the Output Compare Register 1. For a

complete description, please, refer above in sub-

stituting the appropriate index in the bit and regis-

ter names.

4.3.2.7 Software Force Compare

The force compare capability main purpose is to

facilitate fixed frequency generation.

When the Force Output Level 1 bit (FOLV1) of

TCR is written to 1, OLVL1 is copied to pin

OCMP1. To provide this capability, internal logic

allows a single instruction to change OLVL1 and

causes a forced compare with the new value of

OLVL1. OCF1 is not affected and thus, no inter-

rupt request is generated.

Figure 19. Input Capture Timing Diagram

Note: The Diagram represents a situation with rising edge sensitivity (IEDG1 = 1). The capture operation is performed at the next rising edge

of T11, if the action edge of ICAP happened before the previous T10 falling edge.

3456

789

ICAP FLAG

ICAP REGISTER

T10

T11

FF01h

FF02h

FF03h

VR001180

COUNTER REGISTER

ICAP PIN (see note)

TIMER INTERNAL

CLOCKS

CPU CLOCK STANDARD

16-BIT TIMER (Continued)

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