ATR0621 datasheet(9/20 Pages) ATMEL

9 / 20 page

4890AS–GPS–09/05

ATR0621 [Preliminary]

SPI

SCK

SPI Clock

I/O

–

PIO-controlled after reset

MOSI

Master Out Slave In

I/O

–

PIO-controlled after reset

MISO

Master In Slave Out

I/O

–

PIO-controlled after reset

NSS/NPCS0

Slave Select

I/O

Low

PIO-controlled after reset

NPCS1-3

Slave Select

Output

Low

PIO-controlled after reset

NWD_OVF

Watchdog Timer Overflow

Output

–

PIO-controlled after reset

PIO

P0-31

Programmable I/O Port

I/O

–

Input after reset

GPS

GPSMODE0-12

GPS Mode

Input

–

PIO-controlled after reset

SIGHI1

Digital IF

Input

–

Interface to ATR0600

SIGLO1

Digital IF

Input

–

Interface to ATR0600

SIGHI2

Digital IF

Input

–

PIO-controlled after reset

SIGLO2

Digital IF

Input

–

PIO-controlled after reset

TIMEPULSE

GPS synchronized time pulse

Output

–

PIO-controlled after reset

JTAG/ICE

TMS

Test Mode Select

Input

–

Internal pull-up resistor

TDI

Test Data In

Input

–

Internal pull-up resistor

TDO

Test Data Out

Output

–

TCK

Test Clock

Input

–

Internal pull-up resistor

NTRST

Test Reset Input

Input

Low

Internal pull-down resistor

DBG_EN

Debug Enable

Input

–

Internal pull-down resistor

CLOCK

CLK23

Clock Input

Input

–

Interface to ATR0600, Schmitt

trigger input

MCLK_OUT

Master Clock Output

Output

–

PIO-controlled after reset

RESET

NRESET

Reset Input

I/O

Low

Open drain with internal pull-up

resistor

POWER

VDD18

Power

–

Core voltage 1.8V

VBAT18

Power

–

Backup power 1.8V

VDDIO

Power

–

Variable I/O voltage

VDD_USB

Power

–

USB voltage 3.0V to 3.6V

GND

Power

–

Ground

LDOBAT

LDOBAT_IN

Power

–

1.8V to 3.6V

VBAT

Power

–

1.95V to 3.6V

VBAT18

Out

–

1.8V backup voltage

LDO18

LDO_IN

LDO In

Power

–

1.65V to 3.6V

LDO_OUT

LDO Out

Power

–

1.8V core voltage, max. 100 mA

LDO_EN

LDO Enable

Input

–

Table 3-2.

ATR0621 Signal Description (Continued)

Module

Name

Function

Type

Active Level Comment

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