Features

– 8192 Search Bins with GPS Acquisition Accelerator

– Accuracy: 2.5m CEP (Stand-Alone, S/A off)

– Time to First Fix: 34s (Cold Start)

– Acquisition Sensitivity: –140 dBm

– Tracking Sensitivity: –150 dBm

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Embedded ICE (In-circuit Emulator)

– Maximum External Address Space of 8 Mbytes

– Up to 4 Chip Selects

– Software Programmable 8-bit/16-bit External Data Bus

– 2 External Interrupts

– Universal Serial Bus (USB) V2.0 Full-speed Device Specification Compliant

– Embedded USB V2.0 Full-speed Transceiver

– Suspend/Resume Logic

– Ping-pong Mode for Isochronous and Bulk Endpoints

– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART

– 2 Dedicated Peripheral Data Controller (PDC) Channels

– 8-bit to 16-bit Programmable Data Length

– 4 External Slave Chip Selects

– Peripherals Can Be Deactivated Individually

– Geared Master Clock to Reduce Power Consumption

– Sleep State with Disabled Master Clock

– Hibernate State with 32.768 kHz Master Clock

× 9 mm 100-pin BGA Package (LFBGA100)

Electrostatic sensitive device.

Observe precautions for handling.

GPS Baseband

Processor

ATR0621

Summary

Preliminary

Rev. 4890AS–GPS–09/05

Note: This is a summary document. A complete document

is available under NDA. For more information, please con-

tact your local Atmel sales office.