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4890AS–GPS–09/05

ATR0621 [Preliminary]

2.

Architectural Overview

2.1

Description

The ATR0621 architecture consists of two main buses, the Advanced System Bus (ASB) and

the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-

faces the processor with the on-chip 32-bit memories and the external memories and devices

by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip

peripherals and is optimized for low power consumption. The AMBA Bridge provides an inter-

face between the ASB and the APB.

An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip

USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most

importantly, the PDC2 removes the processor interrupt handling overhead and significantly

reduces the number of clock cycles required for a data transfer. It can transfer up to 64K con-

tiguous bytes without reprogramming the starting address. As a result, the performance of the

microcontroller is increased and the power consumption reduced.

The ATR0621 peripherals are designed to be easily programmable with a minimum number of

instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of

the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address

space.) The peripheral base address is the lowest address of its memory space. The periph-

eral register set is composed of control, mode, data, status, and interrupt registers.

To maximize the efficiency of bit manipulation, frequently written registers are mapped into

three memory locations. The first address is used to set the individual register bits, the second

resets the bits, and the third address reads the value stored in the register. A bit can be set or

reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0”

has no effect. Individual bits can thus be modified without having to use costly read-modify-

write and complex bit-manipulation instructions.

All of the external signals of the on-chip peripherals are under the control of the Parallel I/O

(PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin

or generate an interrupt on a signal change. After reset, the user must carefully program the

PIO2 Controller in order to define which peripheral signals are connected with off-chip logic.

The ARM7TDMI

The processor's internal architecture and the ARM

described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are

described in detail in the ATR0621 full datasheet. The electrical and mechanical characteris-

tics are also documented in the ATR0621 full datasheet.

The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of

the ATR0621.

Features of the ROM firmware are described in software documentation available from u-blox

AG.