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PI2DPX2020 数据表(PDF) 20 Page - Diodes Incorporated

部件名 PI2DPX2020
功能描述  1.8V 20Gbps USB4/TBT4/DP2.0 DP-Alt Linear ReDriver with AUX-SBU Switch
PDF  39 Pages
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制造商  DIODES [Diodes Incorporated]
网页  http://www.diodes.com
标志 DIODES - Diodes Incorporated

PI2DPX2020 数据表(HTML) 20 Page - Diodes Incorporated

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A Product Line of
Diodes Incorporated
PI2DPX2020
20
www.diodes.com
July 2022
Diodes Incorporated
PI2DPX2020
Document Number DS43506 Rev 5-2
I2C Electrical Specification and Timing
Characteristics of the SDA and SCL I/O Stages
Symbol
Parameter
Conditions
This Silicon
Fast-mode Plus Spec
Units
Min.
Max.
Min.
Max.
VIL
LOW-level input voltage
−0.5
0.3VDD
−0.5
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
0.7VDD
V
Vhys
Hysteresis of Schmitt trigger
inputs
0.05VDD
0.05VDD
V
VOL1
LOW-level output voltage 1
Open-drain or open-col-
lector at 3mA sink current;
VDD >2V
0
0.4
0
0.4
V
IOL
LOW-level output current
VOL =0.4V
20
20
mA
tof
Output fall time from VIH-
min to VILmax
12
120
20×(VDD
/5.5V)
120
ns
tSP
Pulse width of spikes that
must be suppressed by the
input filter
0
50
0
50
ns
Ii
Input current each I/O pin
0.1VDD <VI < 0.9VDDmax
−10
+10
−10
+10
uA
Ci
Capacitance for each I/O pin
10
10
pF
Characteristics of the SDA and SCL Bus Lines the Devices
Symbol
Parameter
Conditions
This Silicon
Fast-mode Plus Spec
Units
Min.
Max.
Min.
Max.
fSCL
SCL clock frequency
10
1000
0
1000
kHz
tHD;STA
Hold time (repeated) START
condition
After this period, the first
clock pulse is generated.
0.26
-
0.26
-
us
tLOW
LOW period of the SCL clock
0.5
-
0.5
-
us
tHIGH
HIGH period of the SCL
clock
0.26
-
0.26
-
us
tSU;STA
Set-up time for a repeated
START condition
0.26
-
0.26
-
us
tSU;DAT
Data set-up time
50
50
-
ns
tr
Rise time of both SDA and
SCL signals
120
-
120
ns
tf
Fall time of both SDA and
SCL signals
12
120
20×(VDD
/5.5V)
120
ns
tSU;STO
Set-up time for STOP condi-
tion
0.26
-
0.26
-
us
tBUF
Bus free time between a
STOP and START condition
0.5
-
0.5
-
us



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