A Product Line of

Diodes Incorporated

PI2DPX2020

23

www.diodes.com

July 2022

Diodes Incorporated

PI2DPX2020

Document Number DS43506 Rev 5-2

Symbol Parameter

Conditions

Standard-mode

Fast-mode

Fast-mode Plus

Units

Min.

Max.

Min.

Max.

Min.

Max.

tVD;ACK Data valid acknowledge

time(12)

3.45(4)

0.9(4)

0.45(4)

µs

VnL

Noise margin at the LOW level

For each connected

device (including

hysteresis)

0.1VDD

0.1VDD

0.1VDD

V

VnH

Noise margin at the HIGH

level

For each connected

device (including

hysteresis)

0.2VDD

0.2VDD

0.2VDD

V

Note:

1. All values referred to VIH(min) (0.3VDD) and VIL(max) (0.7VDD) levels.

2. tHD:DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

3. A device must internally provide a hold time of at least 300ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of

the falling edge of SCL.

4. The maximum tHD:DAT could be 3.45µs and 0.9µs for Standard-mode and Fast-mode, but must be less than the maximum of tVD:DAT or tVD:ACK by a transition

time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid

by the set-up time before it releases the clock.

5. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU:DAT 250ns must then be met. This will automatically be the

case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line tr(max) + tSU:DAT = 1000 + 250 = 1250ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge

timing must meet this set-up time.

6. If mixed with Hs-mode device, faster fall times according to Table XX are allowed.

7. The maximum tf for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tf is specified are 250ns. This allows series

protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

8. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering

bus timing.

9. Necessary to be backwards compatible to Fast-mode.

10. The maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application. Section XX dis-

cusses techniques for coping with higher bus capacitances.

11. tVS:DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

12. tVS:ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

Figure 12. Definition of timing for F/S-mode devices on the I2C bus.