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PI2DPX2020 数据表(PDF) 32 Page - Diodes Incorporated

部件名 PI2DPX2020
功能描述  1.8V 20Gbps USB4/TBT4/DP2.0 DP-Alt Linear ReDriver with AUX-SBU Switch
PDF  39 Pages
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制造商  DIODES [Diodes Incorporated]
网页  http://www.diodes.com
标志 DIODES - Diodes Incorporated

PI2DPX2020 数据表(HTML) 32 Page - Diodes Incorporated

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A Product Line of
Diodes Incorporated
PI2DPX2020
32
www.diodes.com
July 2022
Diodes Incorporated
PI2DPX2020
Document Number DS43506 Rev 5-2
BYTE 18 (DPCD Address 00101h: Lane Count Set)
Bit
Type
Power-up Condition
Comment
7
RO
0
LANE_COUNT_SET
Main-Link Lane Count = Value.
Bit<4:0>LANE_COUNT_SET
Three values are supported. All other values are RESERVED.
Note: Because the upstream device is required to set this value within the
MAX_LINK_RATE register (DPCD Address 00001h), there is no power-on
reset default value for this field. It is suggested to program this field to 1h.
(See the Note within the description for the LINK_BW_SET register (DPCD
Address 00100h.)
1h = 1 lane (Lane 0 only)
2h = 2 lanes (Lanes 0 and 1 only)
4h = 4 lanes
A Source device may choose any lane count as long as it does not exceed the
capability of the DPRX.
For DPCD Ver.1.0:
Bits <7:5> = RESERVED. Read all 0’s.
For DPCD Ver.1.1:
Bits <6:5> = RESERVED. Read all 0’s.
Bit 7 = ENHANCED_FRAME_EN
0 = Enhanced Framing symbol sequence is not enabled.
1 = Enhanced Framing symbol sequence for BS and SR is enabled. Appli-
cable to SST-only mode. A DPTX must set this bit to 1 when the DPRX has
the ENHANCED_FRAME_CAP bit in the MAX_LANE_COUNT register
(DPCD Address 00002h, bit 7) set to 1.
6
RO
0
5
RO
0
4
RO
0
3
RO
0
2
RO
1
1
RO
0
0
RO
0
BYTE 19 - 30 (Reserved)
BYTE 31 (DPCD Address 00600h: SET DP Power)
Bit
Type
Power-up Condition
Comment
7
RO
0
SET_POWER_STATE
Bit 2:0
001 = Set local Sink device and all downstream Sink devices to D0 (normal
operation mode).
010 = Set local Sink device and all downstream Sink devices to D3 (power-
down mode).
101 = Set Main-Link for local Sink device and all downstream Sink devices
to D3 (power-down mode), keep AUX block fully powered, ready to reply
within a Response Timeout period of 300us.
All other values are RESERVED.
6
RO
0
5
RO
0
4
RO
0
3
RO
0
2
RO
0
1
RO
0
0
RO
1



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