FT902Q-R datasheet(28/67 Pages) BRIDGETEK

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FT900

/1/2/3 Revision C Embedded Microcontroller Datasheet

Version 1.0

Document No. BRT_000172 Clearance No.: BRT#087



Supports single shot transmission.



Supports an abort transmission feature.



Readable error counters and last error code capture supported.



4.11

Real Time Clock

The Real Time Clock (RTC) runs off a dedicated 32.768 kHz oscillator with its own power rail which can be

connected to a separate battery via the VBAT pin.

4.11.1

Features



Built-in Clock Stabilizer for the 32.768 kHz input



Records system sleep time



Supports Date and Time format in BCD



Counts Second, Minute, Hour, Day, Date of the Month, Month and Year with Leap-Year

Compensation Valid up to 2199



Supports two configurable Time-of-Day Alarms



Supports interrupt for two configurable alarm events



Supports On-Chip Digital Trimming with Auto Calibration

4.12

One-Wire Debugger Interface

The Debugger interface provides the capability, over a One-Wire half duplex serial link, to access memory

mapped address space, such as the FT900 Flash memory, program memory, data memory and I/O

memory. However, there is no transfer capability from any of the internal memory to the debugger

interface.

4.12.1

Features



Single wire half duplex link that has one Start, eight Data and one Stop bits at a 1M bit/s rate.



Supports debugger command read / write operation with variable data transfer.



Supports CHIP ID read out.



Supports checksum check by Flash memory operation.



Supports CPU software debugging to execute Run, Stop, Step, Halt, Set software breakpoint, etc.

operations.



Use semaphore flag to control resource allocated by CPU or Debugger.

4.13

SPI Interface

The FT900/1/2/3 series contains an SPI master and SPI0, SPI1 slave controllers. SPI is a full duplex

serial interface designed to handle multiple masters and slaves connected to a given bus.

4.13.1

Features



Maximum SPI data bit rate 50MHz in master and 25MHz in slave modes.



Full duplex synchronous serial data transfer.



Compliant with SPI specification, support four transfer formats.



SPI master supports Single, Dual and Quad SPI transfer.



SPI0, SPI1 slave support Single transfer only.



Support SPI mode and FIFO mode operations.



Multi-master system supported.



Support bus error detection.



SPI master can address up to 4 SPI slave devices.



Support 16/64 Bytes receiver and 16/64 Bytes transmitter FIFO respectively.

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