TDA4VE...ALZQ1 datasheet(122/251 Pages) TI

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J7VCL_ELCH_03

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)

(C)

(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDA_3P3_USB

(E)

(C)

(F)

(VDDA_MCU_PLLGRP0,

VDDA_MCU_TEMP, VDDA_ADC_MCU,

VDDA_POR_WKUP, VDDA_WKUP)

(G)

VDD_MCU ,VDD_MCU_WAKE1, VDDAR_MCU

(J)

VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,

VDDA_0P8_SERDES_C, VDDA_0P8_USB

VDDAR_CORE, VDDAR_CPU

MCU_PORz

(K)(L)

PORz

(K)(L)

OSC1_XI, OSC1_XO

(optional)

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

WKUP_OSC0_XI, WKUP_OSC0_XO

VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C

MCU_BOOTMODE[9:0], BOOTMODE[7:0]

(K)

Valid Configuration

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)

(D)

(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6)

VDDS_MMC0

(E)

(D),

VDDA_OSC1, VDDA_PLLGRP8,

VDDA_PLLGRP6, VDDA_PLLGRP4,

VDDA_PLLGRP0, VDDA_TEMP1, VDDA_TEMP0,

VDD_CPU

Note 1

(VDDA_1P8_SERDES, VDDA_1P8_USB)

(H)

Note 1

VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0

(I)

T1Time stamp markers:

•

T0 – All 3.3-V voltages start supply ramp-up to VOPR MIN. (0 ms)

•

T1 – All 1.8-V voltages start supply ramp-up to VOPR MIN. (2 ms)

•

T2 – All core voltages start supply ramp-up to VOPR MIN. (3 ms)

•

T3 – All RAM array voltages start supply ramp-up to VOPR MIN. (4 ms)

•

T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13 ms)

Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.

A few supplies could have varying start times between T0 to T1 due to PDN designs using different power resources with varying

turn-on & ramp-up time delays.

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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