TDA4VE...ALZQ1 datasheet(124/251 Pages) TI

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7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing

Figure 7-6 describes the device power-down sequencing.

J7VCL_ELCH_04

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)

(B)

(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDA_3P3_USB

(D)

(B)

(E)

(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP,

VDDA_ADC_MCU, VDDA_POR_WKUP, VDDA_WKUP)

(F)

VDD_MCU

(8)

VDD MCU WAKE

VDDAR MCU

VDDAR_CORE, VDDAR_CPU

MCU_PORz

(J)

PORz

(J)

OSC1_XI, OSC1_XO

(optional)

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

WKUP_OSC0_XI, WKUP_OSC0_XO

VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)

(C)

(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6)

VDDS_MMC0

(D)

(C),

VDDA_OSC1, VDDA_PLLGRP8,

VDDA_PLLGRP6, VDDA_PLLGRP4,

VDDA_PLLGRP0, VDDA_TEMP01, VDDA_TEMP0,

VDD_CPU

(VDDA_1P8_SERDES, VDDA_1P8_USB)

(G)

(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)

(H)

Δ1

MCU_BOOTMODE[9:0], BOOTMODE[7:0]

VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,

VDDA_0P8_SERDES_C, VDDA_0P8_USB

Valid Configuration

Time stamp markers:

•

T0 – MCU_PORz and PORz assert low to put all processor resources in safe state. (0 ms)

•

T1 – Main DDR, SRAM Core, and SRAM CPU power domains start ramp-down. (0.5 ms)

•

T2 – All core voltages start supply ramp-down. (2.5 ms)

•

T3 – All 1.8V voltages start supply ramp-down. (3.0 ms)

•

T4 – All 3.3V voltages start supply ramp-down. (3.5 ms)

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.

Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.

When eMMC memories are used, Main 1.8-V supplies could have a ramp-down aligned to T1 due to PDN designs grouping supplies

with VDD_MMC0.

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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