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TDA4VE...ALZQ1 数据表(PDF) 226 Page - Texas Instruments |
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TDA4VE...ALZQ1 数据表(HTML) 226 Page - Texas Instruments |
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226 / 251 page  Table 7-89. OSPI0/1 Switching Characteristics – Tap DDR Mode see Figure 7-105 NO. PARAMETER MODE MIN MAX UNIT O1 tc(CLK) Cycle time, OSPI0/1_CLK 40 ns O2 tw(CLKL) Pulse duration, OSPI0/1_CLK low ((0.475P(1)) - 0.3) ns O3 tw(CLKH) Pulse duration, OSPI0/1_CLK high ((0.475P(1)) - 0.3) ns O4 td(CSn-CLK) Delay time, OSPI0/1_CSn[3:0] active edge to OSPI0/1_CLK rising edge ((0.475P(1)) + ((0.975M(2)R(4)) - 1) ((0.525P(1)) + (1.025M(2)R(4)) + 1) ns O5 td(CLK-CSn) Delay time, OSPI0/1_CLK rising edge to OSPI0/1_CSn[3:0] inactive edge ((0.475P(1)) + (0.975N(3)R(4)) - 1) ((0.525P(1)) + (1.025N(3)R(4)) + 1) ns O6 td(CLK-D) Delay time, OSPI0/1_CLK active edge to OSPI0/1_D[7:0] transition (–17.94 + (0.975T(5)R(4))) (–1.56 + (1.025T(5)R(4))) ns (1) P = CLK cycle time = SCLK period in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = refclk cycle time in ns (5) T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] OSPI_CLK OSPI_TIMING_01 OSPI_CSn O6 O3 O2 O1 O5 OSPI_D[i:0] O6 O4 Figure 7-105. OSPI0/1 Switching Characteristics – Tap DDR, No Loopback 7.10.5.20 OLDI 7.10.5.20.1 OLDI Switching Characteristics NO. PARAMETER MODE MIN MAX UNIT O1 LVDS Low-to-High Transition Time max IOSET1 0.18 0.5 ns O2 LVDS high-to-low Transition Time max IOSET1 0.18 0.5 ns O3 Transmitter Output Bit Width min IOSET1 1 1 UI O4 Transmitter Pulse Positions – Normalized IOSET1 0.25 0.75 ns O5 Variation in transmitter pulse position across Bit 7:0 pulse positions IOSET1 -0.06 0.06 ns O6 TxOut Channel to Channel Skew IOSET1 110 ns O7 Transmitter Jitter Cycle-to-Cycle IOSET1 0.028 0.035 ns O8 Input Total Jitter Tolerance (Includes data to clock skew, pulse position variation.) IOSET1 0.25 ns TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 226 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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