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TDA4VE...ALZQ1 数据表(PDF) 229 Page - Texas Instruments |
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TDA4VE...ALZQ1 数据表(HTML) 229 Page - Texas Instruments |
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229 / 251 page  Table 7-91. UART Timing Conditions (continued) PARAMETER DESCRIPTION MIN MAX UNIT CL Output load capacitance 1 30(1) pF (1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore, it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point where the minimum data valid time of the attached device is violated. Section 7.10.5.23.1, Section 7.10.5.23.2, and Figure 7-110 present timing requirements and switching characteristics for UART interface. 7.10.5.23.1 Timing Requirements for UART NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT 4 tw(rxd) Pulse width, receive data bit, high or low 0.95U(1) (2) 1.05U(1) (2) ns 5 tw(rxdS) Pulse width, receive start bit, low 0.95U(1) (2) ns (1) U = UART baud time = 1/Programmed baud rate (2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL. 7.10.5.23.2 UART Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT f(baud) Maximum programmable baud rate 12 Mbps 2 tw(TX) Pulse width, transmit data bit, high or low U - 2(1) U + 2(1) ns 3 tw(RTS) Pulse width, transmit start bit, high or low U - 2(1) ns (1) U = UART baud time = 1/Programmed baud rate UARTi_TXD 4 Start Bit Data Bits 3 UARTi_RXD 2 Data Bits Bit Start 1 V IH V IL UART_TIMING_01_RCVRVIHVIL Figure 7-110. UART Timing For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter in the device TRM. 7.10.5.24 USB The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the specification for timing details. The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0. Refer to the specification for timing details. www.ti.com TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 229 Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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