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AM69AX 数据表(PDF) 7 Page - Texas Instruments |
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AM69AX 数据表(HTML) 7 Page - Texas Instruments |
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7 / 299 page  Table 5-1. Device Comparison (continued) FEATURES(7) REFERENCE NAME AM69A9 AM69A7 Capture Subsystem with Camera Serial Interface (CSI2) CSI2.0 4L RX 3 3 CSI2.0 4L TX 2 2 Multichannel Serial Peripheral Interface MCSPI 11 11 Multichannel Audio Serial Port MCASP0 16 Serializers 16 Serializers MCASP1 5 Serializers 5 Serializers MCASP2 5 Serializers 5 Serializers MCASP3 3 Serializers 3 Serializers MCASP4 5 Serializers 5 Serializers MultiMedia Card/ Secure Digital Interface MMCSD0 eMMC (8-bits) eMMC (8-bits) MMCSD1 SD/SDIO (4-bits) SD/SDIO (4-bits) Universal Flash Storage UFS 2L No No Flash Subsystem (FSS) OSPI0 8-bits(6) 8-bits(6) OSPI1(8) 4-bits 4-bits HyperBus Yes(6) Yes(6) 4x PCI Express Port with Integrated PHY PCIE 2x4L or 4x2L(4) 2x4L or 4x2L(4) Hyperlink HYP No(9) No(9) Ethernet Interfaces MCU CPSW2G RMII or RGMII(5) RMII or RGMII(5) MAIN CPSW2G RMII or RGMII(5) RMII or RGMII(5) CPSW9G 8 port SERDES(4) 8 port SERDES(4) General-Purpose Timers TIMER 30 30 Enhanced High Resolution Pulse-Width Modulator Module eHRPWM 6 6 Enhanced Capture Module eCAP 3 3 Enhanced Quadrature Encoder Pulse Module eQEP 3 3 Universal Asynchronous Receiver and Transmitter UART 12 12 Universal Serial Bus (USB3.1) SuperSpeed Dual- Role-Device (DRD) Ports with SS PHY USB0 Yes(4) Yes(4) (1) Functional Safety is not supported on this device family, if interested in this feature, please see the TDA4VH device family. (2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as indicated by the Device Type (Y) identifier in the Table 10-1, Nomenclature Description table (3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Device Naming Convention table (4) DP, SGMII, USB3.0, and PCIE share total of 16 SerDes lanes. (5) AM69A CPSW supports up to 8 ports using the following instances and signals and modes of operation: • PORT1 Signals: SGMII1, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII • PORT2 Signals: SGMII2, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII • PORTn (n=3 thru 8) Signals: SGMIIn, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII If QSGMII is used on any SGMII Port 1 thru 4, then SGMII1/2/3/4 cannot be used for Ethernet functionality since all 4 internal CPSW ports map to the selected QSGMII SERDES port. If QSGMII is used on any SGMII Port 5 thru 8, then SGMII5/6/7/8 cannot be used for Ethernet functionality since all 4 internal CPSW ports map to the selected QSGMII SERDES port. (6) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1. (7) J784S4 is the base part number for the superset device. Software should constrain the features used to match the intended production device. (8) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts. (9) Hyperlink is not supported on this SoC. System designs should not use the signals HYP_*, HYP0_*, HYP1_*. (10) MCU_R5FSS0 includes Dual-Core R5F that provides Device Management functionality, and is reserved for executing TI provided code. R5FSS1 is a Dual-Core R5F that provides Multimedia Control functionality, and is reserved for executing TI provided code. (11) The Deep Learning Accelerator C7x + MMA are reserved for executing TI provided code, and are not available for custom code. www.ti.com AM69A SPRSP92 – FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: AM69A |
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